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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
lib/Target/AMDGPU/R600InstrInfo.h 295 int getOperandIdx(unsigned Opcode, unsigned Op) const;
References
lib/Target/AMDGPU/R600ClauseMergePass.cpp 87 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT))
94 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled))
100 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT);
119 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT);
131 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0);
133 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0);
135 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0);
147 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE1);
149 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK1);
151 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR1);
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 379 TII->getOperandIdx(MI.getOpcode(), R600::OpName::literal));
lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp 98 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst);
104 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(),
106 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(),
159 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src0))
162 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src1))
lib/Target/AMDGPU/R600ISelLowering.cpp 302 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst);
2104 bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1;
2115 TII->getOperandIdx(Opcode, R600::OpName::src0),
2116 TII->getOperandIdx(Opcode, R600::OpName::src1),
2117 TII->getOperandIdx(Opcode, R600::OpName::src2),
2118 TII->getOperandIdx(Opcode, R600::OpName::src0_X),
2119 TII->getOperandIdx(Opcode, R600::OpName::src0_Y),
2120 TII->getOperandIdx(Opcode, R600::OpName::src0_Z),
2121 TII->getOperandIdx(Opcode, R600::OpName::src0_W),
2122 TII->getOperandIdx(Opcode, R600::OpName::src1_X),
2123 TII->getOperandIdx(Opcode, R600::OpName::src1_Y),
2124 TII->getOperandIdx(Opcode, R600::OpName::src1_Z),
2125 TII->getOperandIdx(Opcode, R600::OpName::src1_W)
2226 TII->getOperandIdx(Opcode, R600::OpName::src0_X),
2227 TII->getOperandIdx(Opcode, R600::OpName::src0_Y),
2228 TII->getOperandIdx(Opcode, R600::OpName::src0_Z),
2229 TII->getOperandIdx(Opcode, R600::OpName::src0_W),
2230 TII->getOperandIdx(Opcode, R600::OpName::src1_X),
2231 TII->getOperandIdx(Opcode, R600::OpName::src1_Y),
2232 TII->getOperandIdx(Opcode, R600::OpName::src1_Z),
2233 TII->getOperandIdx(Opcode, R600::OpName::src1_W)
2236 TII->getOperandIdx(Opcode, R600::OpName::src0_neg_X),
2237 TII->getOperandIdx(Opcode, R600::OpName::src0_neg_Y),
2238 TII->getOperandIdx(Opcode, R600::OpName::src0_neg_Z),
2239 TII->getOperandIdx(Opcode, R600::OpName::src0_neg_W),
2240 TII->getOperandIdx(Opcode, R600::OpName::src1_neg_X),
2241 TII->getOperandIdx(Opcode, R600::OpName::src1_neg_Y),
2242 TII->getOperandIdx(Opcode, R600::OpName::src1_neg_Z),
2243 TII->getOperandIdx(Opcode, R600::OpName::src1_neg_W)
2246 TII->getOperandIdx(Opcode, R600::OpName::src0_abs_X),
2247 TII->getOperandIdx(Opcode, R600::OpName::src0_abs_Y),
2248 TII->getOperandIdx(Opcode, R600::OpName::src0_abs_Z),
2249 TII->getOperandIdx(Opcode, R600::OpName::src0_abs_W),
2250 TII->getOperandIdx(Opcode, R600::OpName::src1_abs_X),
2251 TII->getOperandIdx(Opcode, R600::OpName::src1_abs_Y),
2252 TII->getOperandIdx(Opcode, R600::OpName::src1_abs_Z),
2253 TII->getOperandIdx(Opcode, R600::OpName::src1_abs_W)
2261 bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1;
2279 TII->getOperandIdx(Opcode, R600::OpName::src0),
2280 TII->getOperandIdx(Opcode, R600::OpName::src1),
2281 TII->getOperandIdx(Opcode, R600::OpName::src2)
2284 TII->getOperandIdx(Opcode, R600::OpName::src0_neg),
2285 TII->getOperandIdx(Opcode, R600::OpName::src1_neg),
2286 TII->getOperandIdx(Opcode, R600::OpName::src2_neg)
2289 TII->getOperandIdx(Opcode, R600::OpName::src0_abs),
2290 TII->getOperandIdx(Opcode, R600::OpName::src1_abs),
2300 bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1;
2302 int ImmIdx = TII->getOperandIdx(Opcode, R600::OpName::literal);
lib/Target/AMDGPU/R600InstrInfo.cpp 156 return isLDSInstr(Opcode) && getOperandIdx(Opcode, R600::OpName::dst) != -1;
270 if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) {
271 return getOperandIdx(Opcode, Row[1]);
295 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][0]));
299 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));
315 int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]);
322 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));
328 MI.getOperand(getOperandIdx(MI.getOpcode(), R600::OpName::literal));
548 unsigned Op = getOperandIdx(IG[i]->getOpcode(),
1327 getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src0, Slot)));
1329 getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src1, Slot)));
1349 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
1351 MIB->getOperand(getOperandIdx(Opcode, R600::OpName::pred_sel))
1356 getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
1381 return getOperandIdx(MI.getOpcode(), Op);
lib/Target/AMDGPU/R600MachineScheduler.cpp 356 int DstIndex = TII->getOperandIdx(MI->getOpcode(), R600::OpName::dst);
lib/Target/AMDGPU/R600Packetizer.cpp 86 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write);
89 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst);
136 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Ops[i]);
187 int OpI = TII->getOperandIdx(MII->getOpcode(), R600::OpName::pred_sel),
188 OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600::OpName::pred_sel);
222 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), R600::OpName::last);
302 unsigned Op = TII->getOperandIdx(MI->getOpcode(),
307 TII->getOperandIdx(MI.getOpcode(), R600::OpName::bank_swizzle);