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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc114563 case 3: return (!Subtarget->isSTRQroSlow() || MF->getFunction().hasOptSize());
114564 case 4: return (Subtarget->isLittleEndian()) && (!Subtarget->isSTRQroSlow() || MF->getFunction().hasOptSize());
114579 case 19: return ( !MF->getFunction().hasFnAttribute("branch-target-enforcement") );
114580 case 20: return ( MF->getFunction().hasFnAttribute("branch-target-enforcement") );
114582 case 22: return (!MF->getFunction().hasOptNone() || MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) || !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized));
114582 case 22: return (!MF->getFunction().hasOptNone() || MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) || !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized));
114582 case 22: return (!MF->getFunction().hasOptNone() || MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) || !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized));
114586 case 26: return (!MF->getFunction().hasOptSize());
114587 case 27: return (!MF->getFunction().hasOptSize()) && (Subtarget->useAlternateSExtLoadCVTF32Pattern());
114925 const DataLayout &DL = MF->getDataLayout();
gen/lib/Target/ARM/ARMGenDAGISel.inc53895 case 34: return (Subtarget->hasNEON()) && (MF->getDataLayout().isLittleEndian());
53896 case 35: return (Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian());
53898 case 37: return (Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isLittleEndian());
53899 case 38: return (Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian());
53918 case 57: return (MF->getDataLayout().isLittleEndian()) && (Subtarget->isThumb()) && (Subtarget->isThumb1Only());
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc72225 case 1: return (HST->useHVXOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72227 case 3: return (HST->useHVXOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
72230 case 6: return (HST->useHVXOps()) && (HST->useHVX64BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
72231 case 7: return (HST->useHVXOps()) && (HST->useHVX64BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72233 case 9: return (HST->useHVXOps()) && (HST->useHVX128BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
72234 case 10: return (HST->useHVXOps()) && (HST->useHVX128BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72240 case 16: return (HST->hasV60Ops()) && (HST->useHVX64BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72242 case 18: return (HST->hasV60Ops()) && (HST->useHVX128BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
72243 case 19: return (HST->hasV62Ops()) && (HST->useHVX64BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72245 case 21: return (HST->hasV62Ops()) && (HST->useHVX128BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
72246 case 22: return (HST->hasV65Ops()) && (HST->useHVX64BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72248 case 24: return (HST->hasV65Ops()) && (HST->useHVX128BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
72249 case 25: return (HST->hasV62Ops()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72250 case 26: return (HST->hasV66Ops()) && (HST->useHVX64BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72252 case 28: return (HST->hasV66Ops()) && (HST->useHVX128BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
72253 case 29: return (HST->hasV65Ops()) && (HST->useHVXOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72255 case 31: return (HST->hasV65Ops()) && (HST->useHVXOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13749 case 0: return (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13751 case 2: return (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
13752 case 3: return (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13754 case 5: return (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
13755 case 6: return (MF->getSubtarget().checkFeatures("-64bit"));
13756 case 7: return (MF->getSubtarget().checkFeatures("+64bit"));
13757 case 8: return (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13759 case 10: return (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
13760 case 11: return (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"));
13762 case 13: return (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"));
13764 case 15: return (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"));
13765 case 16: return (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"));
13766 case 17: return (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"));
13768 case 19: return (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13770 case 21: return (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"));
13771 case 22: return (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
13772 case 23: return (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
13773 case 24: return (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
13774 case 25: return (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("-64bit"));
13776 case 27: return (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("+64bit"));
13777 case 28: return (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13779 case 30: return (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13781 case 32: return (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13783 case 34: return (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
13784 case 35: return (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13786 case 37: return (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
gen/lib/Target/X86/X86GenDAGISel.inc253365 case 9: return (!Subtarget->slowIncDec() || MF->getFunction().hasOptSize());
253366 case 10: return (Subtarget->is64Bit()) && (!Subtarget->slowIncDec() || MF->getFunction().hasOptSize());
253377 case 21: return (MF->getFunction().hasMinSize());
253411 case 55: return (MF->getFunction().hasOptSize()) && (Subtarget->hasSSE1() && !Subtarget->hasAVX());
253412 case 56: return (Subtarget->hasAVX()) && (MF->getFunction().hasOptSize());
253467 case 111: return (MF->getFunction().hasOptSize());
253481 case 125: return (MF->getFunction().hasOptSize()) && (Subtarget->hasAVX() && !Subtarget->hasAVX512());
253482 case 126: return (MF->getFunction().hasOptSize() || !Subtarget->hasSSE41()) && (Subtarget->hasSSE1() && !Subtarget->hasAVX());
253483 case 127: return (Subtarget->hasAVX()) && (!MF->getFunction().hasOptSize());
253484 case 128: return (!MF->getFunction().hasOptSize()) && (Subtarget->hasSSE41() && !Subtarget->hasAVX());
253485 case 129: return (Subtarget->hasAVX512()) && (MF->getFunction().hasOptSize());
253486 case 130: return (Subtarget->hasAVX512()) && (!MF->getFunction().hasOptSize());
253513 case 157: return (!Subtarget->is64Bit()) && (MF->getFunction().hasOptSize());
253514 case 158: return (!Subtarget->isTargetWin64() ||Subtarget->getFrameLowering()->hasFP(*MF)) && (MF->getFunction().hasMinSize());
253514 case 158: return (!Subtarget->isTargetWin64() ||Subtarget->getFrameLowering()->hasFP(*MF)) && (MF->getFunction().hasMinSize());
253528 case 172: return (MF->getFunction().hasOptSize()) && (Subtarget->hasSSE41() && !Subtarget->hasAVX());
253533 case 177: return (MF->getFunction().hasOptSize()) && (Subtarget->hasSSE2() && !Subtarget->hasAVX());
253551 case 195: return (Subtarget->hasAVX() && !Subtarget->hasAVX2()) && (MF->getFunction().hasMinSize());
253553 case 197: return (MF->getFunction().hasOptSize() || !Subtarget->hasSSE41()) && (Subtarget->hasSSE2() && !Subtarget->hasAVX());
lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp 44 : Picker(this), InstrItins(IS->MF->getSubtarget().getInstrItineraryData()) {
45 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
60 RegLimit[RC->getID()] = TRI->getRegPressureLimit(RC, *IS->MF);
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp 798 return new ScheduleDAGFast(*IS->MF);
803 return new ScheduleDAGLinearize(*IS->MF);
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 3134 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
3139 new BURegReductionPriorityQueue(*IS->MF, false, false, TII, TRI, nullptr);
3140 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, PQ, OptLevel);
3148 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
3153 new SrcRegReductionPriorityQueue(*IS->MF, false, true, TII, TRI, nullptr);
3154 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, PQ, OptLevel);
3162 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
3168 new HybridBURRPriorityQueue(*IS->MF, true, false, TII, TRI, TLI);
3170 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, PQ, OptLevel);
3178 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
3184 new ILPBURRPriorityQueue(*IS->MF, true, false, TII, TRI, TLI);
3185 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, PQ, OptLevel);
lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp 275 return new ScheduleDAGVLIW(*IS->MF, IS->AA, new ResourcePriorityQueue(IS));
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 9907 MachineFunction::VariableDbgInfoMapTy &DbgDeclareInfo = MF->getVariableDbgInfo();
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 221 << IS.MF->getFunction().getName() << "\n");
238 << IS.MF->getFunction().getName() << "\n");
253 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
421 MF = &mf;
435 TII = MF->getSubtarget().getInstrInfo();
436 TLI = MF->getSubtarget().getTargetLowering();
437 RegInfo = &MF->getRegInfo();
450 CurDAG->init(*MF, *ORE, this, LibInfo,
452 FuncInfo->set(Fn, *MF, CurDAG);
453 SwiftError->setFunction(*MF);
472 MF->setHasInlineAsm(false);
478 if (OptLevel != CodeGenOpt::None && TLI->supportSplitCSR(MF)) {
496 MachineBasicBlock *EntryMBB = &MF->front();
513 MachineRegisterInfo &MRI = MF->getRegInfo();
543 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
574 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
627 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
636 MachineFrameInfo &MFI = MF->getFrameInfo();
637 for (const auto &MBB : *MF) {
638 if (MFI.hasCalls() && MF->hasInlineAsm())
648 MF->setHasInlineAsm(true);
654 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
657 computeUsesMSVCFloatingPoint(TM.getTargetTriple(), Fn, MF->getMMI());
687 TLI->finalizeLowering(*MF);
694 LLVM_DEBUG(MF->print(dbgs()));
802 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
1256 MCSymbol *Label = MF->addLandingPad(MBB);
1267 MF->setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
1373 reportFastISelFailure(*MF, *ORE, R, EnableFastISelAbort > 1);
1512 reportFastISelFailure(*MF, *ORE, R, EnableFastISelAbort > 2);
1561 reportFastISelFailure(*MF, *ORE, R, ShouldAbort);
1603 SP.copyToMachineFrameInfo(MF->getFrameInfo());
1707 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1833 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1886 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1937 MachineInstrBuilder PHI(*MF, MBBI);
3630 MachineFrameInfo &MFI = MF->getFrameInfo();
3650 Msg << "\nIn function: " << MF->getName();
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 280 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF);
lib/Target/ARM/ARMISelDAGToDAG.cpp 1147 MachineFrameInfo &MFI = MF->getFrameInfo();
1168 MachineFrameInfo &MFI = MF->getFrameInfo();
3038 MachineFrameInfo &MFI = MF->getFrameInfo();
4712 MachineRegisterInfo &MRI = MF->getRegInfo();
lib/Target/AVR/AVRISelDAGToDAG.cpp 209 MachineRegisterInfo &RI = MF->getRegInfo();
210 const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>();
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 733 MachineFrameInfo &MFI = MF->getFrameInfo();
751 auto &HMFI = *MF->getInfo<HexagonMachineFunctionInfo>();
1264 auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
1266 if (!HFI.needsAligna(*MF))
1269 MachineFrameInfo &MFI = MF->getFrameInfo();
1270 MachineBasicBlock *EntryBB = &MF->front();
1275 MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);
1283 MachineFrameInfo &MFI = MF->getFrameInfo();
1285 if (!MFI.isFixedObjectIndex(FX) && HFI.needsAligna(*MF))
1567 unsigned StackSize = MF->getFrameInfo().estimateStackSize(*MF);
1567 unsigned StackSize = MF->getFrameInfo().estimateStackSize(*MF);
lib/Target/Mips/MipsISelDAGToDAG.cpp 68 Register GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 1226 IntegerType::get(MF->getFunction().getContext(), 32);
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 57 return Subtarget->getTargetLowering()->useF32FTZ(*MF);
62 return TL->allowFMA(*MF, OptLevel);
67 return TL->allowUnsafeFPMath(*MF);
863 if (canLowerToLDG(LD, *Subtarget, CodeAddrSpace, MF)) {
1007 if (canLowerToLDG(MemSD, *Subtarget, CodeAddrSpace, MF)) {
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 321 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
434 MachineBasicBlock &FirstMBB = MF->front();
436 const Module *M = MF->getFunction().getParent();
446 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
454 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
472 MF->getInfo<PPCFunctionInfo>()->setShrinkWrapDisabled(true);
4389 const Module *Mod = MF->getFunction().getParent();
lib/Target/Sparc/SparcISelDAGToDAG.cpp 69 unsigned GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
227 MachineRegisterInfo &MRI = MF->getRegInfo();
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 1666 Subtarget->getRegisterInfo()->getPointerRegClass(*MF);
lib/Target/X86/X86ISelDAGToDAG.cpp 1330 const Function &F = MF->getFunction();
2617 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
2618 auto &DL = MF->getDataLayout();
lib/Target/XCore/XCoreISelDAGToDAG.cpp 153 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF),
153 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF),