reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/MachineRegisterInfo.h

 1031         MachineInstr *P = Op->getParent();
 1034         } while (Op && Op->getParent() == P);
 1037             getBundleStart(Op->getParent()->getIterator());
 1040         } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
 1053       return Op - &Op->getParent()->getOperand(0);
 1137         MachineInstr *P = Op->getParent();
 1140         } while (Op && Op->getParent() == P);
 1143             getBundleStart(Op->getParent()->getIterator());
 1146         } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
 1159         return *getBundleStart(Op->getParent()->getIterator());
 1160       return *Op->getParent();

lib/CodeGen/AggressiveAntiDepBreaker.cpp

  705         MachineInstr *UseMI = Q.second.Operand->getParent();
  723         MachineInstr *DefMI = Q.second.Operand->getParent();
  980               const SUnit *SU = MISUnitMap[Q.second.Operand->getParent()];
  982               UpdateDbgValues(DbgValues, Q.second.Operand->getParent(),

lib/CodeGen/CriticalAntiDepBreaker.cpp

  360     MachineInstr *MI = RefOper->getParent();
  661           const SUnit *SU = MISUnitMap[Q->second->getParent()];
  663           UpdateDbgValues(DbgValues, Q->second->getParent(),

lib/CodeGen/DetectDeadLanes.cpp

  515     const MachineInstr &MI = *Def.getParent();

lib/CodeGen/GlobalISel/CombinerHelper.cpp

   57   assert(FromRegOp.getParent() && "Expected an operand in an MI");
   58   Observer.changingInstr(*FromRegOp.getParent());
   62   Observer.changedInstr(*FromRegOp.getParent());
  325   MachineInstr &UseMI = *UseMO.getParent();
  436       Observer.changingInstr(*UseMO.getParent());
  438       Observer.changedInstr(*UseMO.getParent());
  464     MachineInstr *UseMI = UseMO->getParent();
  485           Observer.erasingInstr(*UseMO->getParent());
  486           UseMO->getParent()->eraseFromParent();
  519       Observer.erasingInstr(*UseMO->getParent());
  520       UseMO->getParent()->eraseFromParent();

lib/CodeGen/GlobalISel/Localizer.cpp

  100   MachineInstr &MIUse = *MOUse.getParent();
  133       LLVM_DEBUG(MachineInstr &MIUse = *MOUse.getParent();
  146         MachineInstr &UseMI = *MOUse.getParent();

lib/CodeGen/IfConversion.cpp

 1494     MachineInstr *OpMI = Op.getParent();

lib/CodeGen/LiveDebugVariables.cpp

  774     MachineInstr *MI = MO.getParent();

lib/CodeGen/LiveInterval.cpp

 1358     MachineInstr *MI = RI->getParent();

lib/CodeGen/LiveIntervals.cpp

  563     MachineInstr *UseMI = MO.getParent();
 1412         const MachineInstr &MI = *MO.getParent();

lib/CodeGen/LiveRangeCalc.cpp

  188     const MachineInstr *MI = MO.getParent();

lib/CodeGen/LiveRangeEdit.cpp

  191     MachineInstr *MI = MO.getParent();

lib/CodeGen/MIRCanonicalizerPass.cpp

  226       MachineInstr *UseInst = UO.getParent();

lib/CodeGen/MIRVRegNamerUtils.cpp

   67         DoesMISideEffect |= (UI->getParent()->getParent() != MI->getParent());
  122       MachineInstr *Def = RI->getParent();

lib/CodeGen/MachineCombiner.cpp

  235     MachineInstr *UseMO = RI->getParent();

lib/CodeGen/MachineInstr.cpp

 2131     auto *DI = MO.getParent();

lib/CodeGen/MachineInstrBundle.cpp

  295       Ops->push_back(std::make_pair(MO.getParent(), getOperandNo()));
  307     else if (!RI.Tied && MO.getParent()->isRegTiedToDefOperand(getOperandNo()))

lib/CodeGen/MachineLoopUtils.cpp

   64           if (Use.getParent()->getParent() != Loop)

lib/CodeGen/MachineRegisterInfo.cpp

  135     MachineInstr *MI = MO.getParent();
  222     MachineInstr *MI = MO->getParent();

lib/CodeGen/MachineSSAUpdater.cpp

  224   MachineInstr *UseMI = U.getParent();

lib/CodeGen/MachineSink.cpp

  266     MachineInstr *UseInst = MO.getParent();
  280     MachineInstr *UseInst = MO.getParent();

lib/CodeGen/MachineTraceMetrics.cpp

  640     DefMI = DefI->getParent();

lib/CodeGen/ModuloSchedule.cpp

   88         MachineInstr *UseMI = UseOp.getParent();
  342     if (O.getParent()->getParent() != MBB)
  356     if (I->getParent()->getParent() != BB)
  743           if (UI->getParent()->getParent() != BB) {
 1147     MachineInstr *UseMI = UseOp.getParent();
 1528     BB = MO->getParent()->getParent();
 1557        << *Source->getParent();

lib/CodeGen/PeepholeOptimizer.cpp

  500     MachineInstr *UseMI = UseMO.getParent();
  573       MachineInstr *UseMI = UseMO->getParent();
 2100         Def = DI->getParent();

lib/CodeGen/ProcessImplicitDefs.cpp

   83       MachineInstr *UserMI = MO.getParent();

lib/CodeGen/RegAllocFast.cpp

  501         MO.getParent()->addRegisterKilled(Alias, TRI, true);

lib/CodeGen/RegisterCoalescer.cpp

  817     MachineInstr *UseMI = MO.getParent();
  866     MachineInstr *UseMI = UseMO.getParent();
 1481       MachineInstr *UseMI = UseMO.getParent();
 1500     if (UseMO.getParent()->isCopyLike())
 1590     const MachineInstr &MI = *MO.getParent();
 1662       MachineInstr &MI = *MO.getParent();

lib/CodeGen/RegisterScavenging.cpp

  632     MachineBasicBlock *MBB = MO.getParent()->getParent();
  637       const MachineInstr &MI = *MO.getParent();
  661   MachineInstr &DefMI = *FirstDef->getParent();

lib/CodeGen/RenameIndependentSubregs.cpp

  221     auto *MI = MO.getParent();
  354         SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent());
  359         SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent()).getDeadSlot();

lib/CodeGen/SelectionDAG/FastISel.cpp

 2360   MachineInstr *User = RI->getParent();

lib/CodeGen/SplitKit.cpp

  178       UseSlots.push_back(LIS.getInstructionIndex(*MO.getParent()).getRegSlot());
 1318     MachineInstr *MI = MO.getParent();

lib/CodeGen/TailDuplicator.cpp

  212         MachineInstr *UseMI = UseMO.getParent();

lib/CodeGen/TwoAddressInstructionPass.cpp

  268       KillMI = UseMO.getParent();
  389     MachineInstr *MI = MO.getParent();
  489     DefMI = Begin->getParent();

lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

  685   MachineInstr *MI = MO.getParent();

lib/Target/AArch64/AArch64InstructionSelector.cpp

 4132   MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
 4181   MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
 4283   MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
 4316   MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
 4342       Root.getParent()->getParent()->getParent()->getRegInfo();
 4386       Root.getParent()->getParent()->getParent()->getRegInfo();
 4461       Root.getParent()->getParent()->getParent()->getRegInfo();
 4575       Root.getParent()->getParent()->getParent()->getRegInfo();

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

  219   MachineInstr *MI = MO.getParent();
  220   MachineBasicBlock *BB = MO.getParent()->getParent();
 1880   getAddrModeInfo(*Root.getParent(), *MRI, AddrInfo);
 1901   getAddrModeInfo(*Root.getParent(), *MRI, AddrInfo);
 1920   MachineInstr *MI = Root.getParent();
 1952   MachineInstr *MI = Root.getParent();
 2002   MachineInstr *MI = Root.getParent();
 2110   MachineInstr *MI = Root.getParent();

lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp

  708         if (UI.getParent()->getParent() != MBB) {
  715           MachineInstr *UseInstr = UI.getParent();
  741       if (!Region->contains(UI.getParent()->getParent())) {
  758       storeLiveOutReg(MBB, RI.getReg(), RI.getParent(), MRI, TRI, PHIInfo);
  762         storeLiveOutReg(MBB, IRI.getReg(), IRI.getParent(), MRI, TRI, PHIInfo);
  800       storeLiveOutRegRegion(TopRegion, RI.getReg(), RI.getParent(), MRI, TRI,
  805         storeLiveOutRegRegion(TopRegion, IRI.getReg(), IRI.getParent(), MRI,
  944     bool IsInside = contains(O.getParent()->getParent());
  945     bool IsLoopPHI = IsInside && (O.getParent()->isPHI() &&
  946                                   O.getParent()->getParent() == getEntry());
 1048             bool UseIsOutsideDefMBB = Def->getParent()->getParent() != MBB;
 1614         if ((*UI).getParent()->getParent() != DefMBB) {
 1959       LLVM_DEBUG(DI->getParent()->dump());
 1965   return (*(MRI->def_begin(Reg))).getParent();
 2109       if (Def->getParent()->getParent() == MBB) {
 2122         if (Def->getParent()->getParent() != MBB) {

lib/Target/AMDGPU/GCNDPPCombine.cpp

  404     if (OldOpndValue->getParent()->getParent() != MovMI.getParent()) {
  454     auto &OrigMI = *Use->getParent();

lib/Target/AMDGPU/GCNNSAReassign.cpp

  205         const MachineInstr *UseInst = U.getParent();

lib/Target/AMDGPU/GCNRegBankReassign.cpp

  436     const MachineInstr *UseInst = U.getParent();

lib/Target/AMDGPU/SIFoldOperands.cpp

  571       MachineInstr *RSUseMI = RSUse->getParent();
  633           FoldCandidate FC = FoldCandidate(Use->getParent(),
  784                                        *OpToFold.getParent(),
  803                                        *OpToFold.getParent(),
  840   const MCInstrDesc &FoldDesc = OpToFold.getParent()->getDesc();
 1133       MachineInstr *UseMI = Use->getParent();
 1186       MachineInstr *UseMI = NonInlineUse->getParent();
 1198       MachineInstr *UseMI = U->getParent();
 1213       MachineInstr *DefMI = Fold.OpToFold->getParent();

lib/Target/AMDGPU/SIInstrInfo.cpp

 5622     MachineInstr &UseMI = *I->getParent();
 5645       } while (I != E && I->getParent() == &UseMI);
 5719          !Op.isDead() && Op.getParent() == &SCCDefInst);

lib/Target/AMDGPU/SIPeepholeSDWA.cpp

  125   MachineInstr *getParentInst() const { return Target->getParent(); }
  308     } else if (ResMO->getParent() != UseMO.getParent()) {
  308     } else if (ResMO->getParent() != UseMO.getParent()) {
  366   return PotentialMO->getParent();
  459   return PotentialMO->getParent();
  738         MachineInstr *Op1Inst = Op1Def->getParent();
  766     MachineInstr *SDWAInst = OrSDWADef->getParent();
  767     MachineInstr *OtherInst = OrOtherDef->getParent();
  897   MachineInstr &MISucc = *NextOp->getParent();

lib/Target/AMDGPU/SIShrinkInstructions.cpp

  479     MachineInstr &MovY = *YTop.getParent();

lib/Target/ARC/ARCOptAddrMode.cpp

  146     MachineInstr *User = it->getParent();

lib/Target/ARM/A15SDOptimizer.cpp

  202       MachineInstr *Def = Op->getParent();

lib/Target/Hexagon/HexagonBitSimplify.cpp

  974     MachineInstr *UseI = I->getParent();
 1218       MachineInstr &UseI = *I->getParent();
 3116       MachineInstr *UseI = UI->getParent();
 3169       MachineInstr *UseI = UI->getParent();

lib/Target/Hexagon/HexagonConstExtenders.cpp

 1859       MachineInstr &UI = *Op.getParent();

lib/Target/Hexagon/HexagonEarlyIfConv.cpp

  393         if (U->getParent()->isPHI())

lib/Target/Hexagon/HexagonExpandCondsets.cpp

  626   MachineInstr *MI = SrcOp.getParent();

lib/Target/Hexagon/HexagonGenInsert.cpp

 1308       UIs.insert(I->getParent());

lib/Target/Hexagon/HexagonGenPredicate.cpp

  238     MachineInstr *UseI = I->getParent();

lib/Target/Hexagon/HexagonHardwareLoops.cpp

 1052     if (std::next(I) != End || !I->getParent()->isPHI())
 1055     MachineInstr *OnePhi = I->getParent();
 1067         MachineInstr *UseMI = Use.getParent();
 1101         MachineInstr *UseMI = I->getParent();

lib/Target/Hexagon/HexagonSplitDouble.cpp

  253       MachineInstr *UseI = Op.getParent();
  438       MachineInstr *UseI = U->getParent();
  548       const MachineInstr *UseI = I->getParent();
 1146       SplitIns.insert(U->getParent());
 1175       Uses.insert(U->getParent());

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

  109     MachineInstr *MI = MO.getParent();

lib/Target/Mips/MipsSERegisterInfo.cpp

  107       const MipsSubtarget &Subtarget = MO.getParent()

lib/Target/PowerPC/PPCPreEmitPeephole.cpp

  140                        << " from " << *DeadOrKillToUnset->getParent());

lib/Target/PowerPC/PPCReduceCRLogicals.cpp

  657     MRI->use_nodbg_begin(CRI.MI->getOperand(0).getReg())->getParent();

lib/Target/PowerPC/PPCVSXFMAMutate.cpp

  285           MachineInstr *UseMI = UseMO.getParent();

lib/Target/RISCV/RISCVMergeBaseOffset.cpp

   89   LoADDI = MRI->use_begin(HiLuiDestReg)->getParent();
  184   MachineInstr &Tail = *MRI->use_begin(DestReg)->getParent();

lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp

  224   MachineFunction &MF = *Cond[1].getParent()->getParent()->getParent();

lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp

  102     MachineInstr *Where = O.getParent();

lib/Target/WebAssembly/WebAssemblyRegColoring.cpp

   71                                             *MO.getParent());

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

  299     const auto &Result = LI.Query(LIS.getInstructionIndex(*I.getParent()));
  512                      LIS.getInstructionIndex(*Op.getParent()).getRegSlot(),
  534   LLVM_DEBUG(dbgs() << " - for use in "; Op.getParent()->dump());
  700     return Range.begin() != Range.end() && Range.begin()->getParent() == Instr;

lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp

   94         if (MO.getParent()->isDebugValue())

lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp

  547         MachineInstr &StoreMI = *StoreMO.getParent();

lib/Target/X86/X86OptimizeLEAs.cpp

  436     MachineInstr &MI = *MO.getParent();
  623           MachineInstr &MI = *MO.getParent();