|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/PowerPC/PPCGenDAGISel.inc19222 /* 48605*/ /*SwitchOpcode*/ 82, TARGET_VAL(ISD::PREFETCH),// ->48690
gen/lib/Target/X86/X86GenDAGISel.inc17741 /* 35790*/ /*SwitchOpcode*/ 50|128,1/*178*/, TARGET_VAL(ISD::PREFETCH),// ->35972
include/llvm/CodeGen/SelectionDAGNodes.h 1406 N->getOpcode() == ISD::PREFETCH ||
1502 N->getOpcode() == ISD::PREFETCH ||
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2709 case ISD::PREFETCH:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 1206 case ISD::PREFETCH: Res = PromoteIntOp_PREFETCH(N, OpNo); break;
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 611 case ISD::PREFETCH: {
6587 Opcode == ISD::PREFETCH ||
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6552 SDValue Result = DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 82 case ISD::PREFETCH: return "Prefetch";
lib/CodeGen/TargetLoweringBase.cpp 750 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 503 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
3057 case ISD::PREFETCH:
lib/Target/ARM/ARMISelLowering.cpp 1247 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
9164 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
lib/Target/Hexagon/HexagonISelLowering.cpp 1301 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
2878 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
lib/Target/PowerPC/PPCISelLowering.cpp 1083 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
lib/Target/SystemZ/SystemZISelLowering.cpp 301 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
5012 case ISD::PREFETCH:
lib/Target/X86/X86ISelLowering.cpp 461 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);