reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/MSP430/MSP430GenDAGISel.inc

 4871          N->getOpcode() != ISD::CopyFromReg;

gen/lib/Target/X86/X86GenDAGISel.inc

253998          N->getOpcode() != ISD::CopyFromReg &&

include/llvm/CodeGen/SelectionDAG.h

  724     return getNode(ISD::CopyFromReg, dl, VTs, Ops);
  734     return getNode(ISD::CopyFromReg, dl, VTs,

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 1851     case ISD::CopyFromReg:
 7179   bool IsCopyOrSelect = BinOpLHSVal.getOpcode() == ISD::CopyFromReg ||
20639     case ISD::CopyFromReg:

lib/CodeGen/SelectionDAG/InstrEmitter.cpp

  341                 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
  946       if (F->getOpcode() == ISD::CopyFromReg) {
 1017   case ISD::CopyFromReg: {

lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp

   84       case ISD::CopyFromReg:    NumberDeps++;  break;
  121       case ISD::CopyFromReg:    break;
  444       case ISD::CopyFromReg:
  549         case ISD::CopyFromReg:

lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

  428   if (N->getOpcode() == ISD::CopyFromReg) {

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

  323     if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) {
  711   case ISD::CopyFromReg:
 1279   if (N->getOpcode() == ISD::CopyFromReg) {
 2271       if (PN->getOpcode() == ISD::CopyFromReg) {
 2362         PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {
 2433       assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&
 2450         Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {
 3001       if (N->getOpcode() == ISD::CopyFromReg &&

lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

  122   if (Def->getOpcode() == ISD::CopyFromReg &&
  547     if (Node->getOpcode() == ISD::CopyFromReg)

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 5395   case ISD::CopyFromReg: {
 8794   if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
 9371   assert((Op.getOpcode() != ISD::CopyFromReg ||
 9871     if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) {
 9880     if (Res.getOpcode() == ISD::CopyFromReg) {

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  171   case ISD::CopyFromReg:                return "CopyFromReg";

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

 2772   case ISD::CopyFromReg:

lib/CodeGen/SelectionDAG/StatepointLowering.cpp

  342       while (CallEnd->getOpcode() == ISD::CopyFromReg)

lib/CodeGen/SelectionDAG/TargetLowering.cpp

   90     if (Value->getOpcode() != ISD::CopyFromReg)

lib/Target/AArch64/AArch64ISelLowering.h

  243          Opc != ISD::CopyFromReg;

lib/Target/AMDGPU/SIISelLowering.cpp

10814   assert(N->getOpcode() == ISD::CopyFromReg);
10821   } while (N->getOpcode() == ISD::CopyFromReg);
10829     case ISD::CopyFromReg:

lib/Target/ARM/ARMISelDAGToDAG.cpp

 2946       if (Ptr.getOpcode() == ISD::CopyFromReg &&

lib/Target/ARM/ARMISelLowering.cpp

 2513   if (Arg.getOpcode() == ISD::CopyFromReg) {
 5675      if (Op.getOpcode() != ISD::CopyFromReg ||
 5684      SDValue Copy = DAG.getNode(ISD::CopyFromReg, SDLoc(Op), MVT::f16, Ops);

lib/Target/AVR/AVRISelDAGToDAG.cpp

  250     if (CopyFromRegOp->getOpcode() == ISD::CopyFromReg) {

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 4198   return AddrOp.getOpcode() == ISD::CopyFromReg;

lib/Target/Sparc/SparcISelLowering.cpp

 1310       if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)

lib/Target/X86/X86ISelDAGToDAG.cpp

  391           if (OtherOp->getOpcode() == ISD::CopyFromReg &&
 2042         RHS.getNode()->getOpcode() == ISD::CopyFromReg ||

lib/Target/X86/X86ISelLowering.cpp

 4233   if (Arg.getOpcode() == ISD::CopyFromReg) {
21489         T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
21489         T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){