|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc85094 /*196947*/ /*SwitchOpcode*/ 74|128,16/*2122*/, TARGET_VAL(ISD::AND),// ->199073
89081 /*204795*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89087 /*204805*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89270 /*205121*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89301 /*205171*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89337 /*205231*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89367 /*205280*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89394 /*205327*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89519 /*205525*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89550 /*205575*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89586 /*205635*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89616 /*205684*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89643 /*205731*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89768 /*205929*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89799 /*205979*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89835 /*206039*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89865 /*206088*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
89892 /*206135*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90017 /*206333*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90048 /*206383*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90084 /*206443*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90114 /*206492*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90141 /*206539*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90266 /*206737*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90297 /*206787*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90333 /*206847*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90363 /*206896*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90390 /*206943*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90515 /*207141*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90546 /*207191*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90582 /*207251*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90612 /*207300*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90639 /*207347*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90764 /*207545*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90795 /*207595*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90831 /*207655*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90861 /*207704*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
90888 /*207751*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
91013 /*207949*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
91044 /*207999*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
91079 /*208056*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
91109 /*208105*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
111168 /*248269*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7722 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc52647 /*114204*/ /*SwitchOpcode*/ 18|128,5/*658*/, TARGET_VAL(ISD::AND),// ->114866
53027 /*115096*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
53034 /*115109*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
53096 /*115262*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
53126 /*115321*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
53152 /*115367*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
53314 /*115901*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
53394 /*116151*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
53505 /*116475*/ /*SwitchOpcode*/ 56|128,23/*3000*/, TARGET_VAL(ISD::AND),// ->119479
53512 /*116489*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
53640 /*116746*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
53694 /*116859*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
53744 /*116969*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
54136 /*118239*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
54320 /*118852*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
54553 /*119574*/ /*SwitchOpcode*/ 24, TARGET_VAL(ISD::AND),// ->119601
57575 /*125919*/ /*SwitchOpcode*/ 40, TARGET_VAL(ISD::AND),// ->125962
57613 /*126009*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
57668 /*126101*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
57717 /*126186*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
57872 /*126661*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
74308 /*164380*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
74329 /*164434*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::AND),// ->164468
74951 /*166018*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 318 /* 848*/ /*SwitchOpcode*/ 84|128,8/*1108*/, TARGET_VAL(ISD::AND),// ->1960
817 /* 2474*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
824 /* 2487*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
950 /* 2997*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1012 /* 3235*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1070 /* 3459*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1356 /* 4701*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1498 /* 5305*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1636 /* 5895*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
2036 /* 7597*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
2205 /* 8350*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
2370 /* 9099*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
3298 /* 13217*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
3741 /* 15228*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
5943 /* 23262*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
6062 /* 23713*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
6175 /* 24156*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
6454 /* 25339*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
gen/lib/Target/ARC/ARCGenDAGISel.inc 581 /* 957*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::AND),// ->1008
gen/lib/Target/ARM/ARMGenDAGISel.inc 1192 /* 2531*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1199 /* 2544*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1458 /* 3050*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1500 /* 3131*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1548 /* 3222*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1591 /* 3304*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1624 /* 3371*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1826 /* 3753*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1868 /* 3834*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1916 /* 3925*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1959 /* 4007*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1992 /* 4074*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
2194 /* 4456*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
2236 /* 4537*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
2284 /* 4628*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
2327 /* 4710*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
2360 /* 4777*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
2562 /* 5159*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
2604 /* 5240*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
2652 /* 5331*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
2695 /* 5413*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8698 /* 18196*/ /*SwitchOpcode*/ 41|128,81/*10409*/, TARGET_VAL(ISD::AND),// ->28609
25727 /* 55518*/ OPC_SwitchOpcode /*2 cases */, 57, TARGET_VAL(ISD::AND),// ->55579
25810 /* 55712*/ /*SwitchOpcode*/ 103, TARGET_VAL(ISD::AND),// ->55818
25953 /* 56047*/ /*SwitchOpcode*/ 70, TARGET_VAL(ISD::AND),// ->56120
26058 /* 56270*/ OPC_SwitchOpcode /*2 cases */, 49, TARGET_VAL(ISD::AND),// ->56323
26111 /* 56383*/ OPC_SwitchOpcode /*2 cases */, 27, TARGET_VAL(ISD::AND),// ->56414
32861 /* 72329*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
gen/lib/Target/ARM/ARMGenFastISel.inc 5162 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6367 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
6722 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/AVR/AVRGenDAGISel.inc 135 /* 143*/ /*SwitchOpcode*/ 58, TARGET_VAL(ISD::AND),// ->204
842 /* 1411*/ /*SwitchOpcode*/ 62, TARGET_VAL(ISD::AND),// ->1476
gen/lib/Target/BPF/BPFGenDAGISel.inc 1450 /* 2499*/ /*SwitchOpcode*/ 100, TARGET_VAL(ISD::AND),// ->2602
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc 7937 /* 15051*/ /*SwitchOpcode*/ 60|128,50/*6460*/, TARGET_VAL(ISD::AND),// ->21515
21268 /* 40549*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
21300 /* 40622*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
22928 /* 43987*/ OPC_SwitchOpcode /*2 cases */, 68, TARGET_VAL(ISD::AND),// ->44059
22976 /* 44098*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
23077 /* 44315*/ OPC_SwitchOpcode /*2 cases */, 48, TARGET_VAL(ISD::AND),// ->44367
23118 /* 44393*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
23230 /* 44616*/ OPC_SwitchOpcode /*3 cases */, 34, TARGET_VAL(ISD::AND),// ->44654
23284 /* 44714*/ OPC_SwitchOpcode /*3 cases */, 36, TARGET_VAL(ISD::AND),// ->44754
23362 /* 44855*/ OPC_SwitchOpcode /*2 cases */, 92, TARGET_VAL(ISD::AND),// ->44951
23432 /* 45014*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
23467 /* 45090*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
23483 /* 45127*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
23518 /* 45203*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
23534 /* 45240*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
23876 /* 45961*/ OPC_SwitchOpcode /*2 cases */, 40, TARGET_VAL(ISD::AND),// ->46005
23921 /* 46051*/ OPC_SwitchOpcode /*2 cases */, 41, TARGET_VAL(ISD::AND),// ->46096
26588 /* 51092*/ /*SwitchOpcode*/ 90|128,37/*4826*/, TARGET_VAL(ISD::AND),// ->55922
26669 /* 51243*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
26701 /* 51316*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
27279 /* 52515*/ OPC_SwitchOpcode /*2 cases */, 68, TARGET_VAL(ISD::AND),// ->52587
27326 /* 52625*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
27530 /* 53093*/ OPC_SwitchOpcode /*3 cases */, 34, TARGET_VAL(ISD::AND),// ->53131
27584 /* 53191*/ OPC_SwitchOpcode /*3 cases */, 36, TARGET_VAL(ISD::AND),// ->53231
27662 /* 53332*/ OPC_SwitchOpcode /*2 cases */, 92, TARGET_VAL(ISD::AND),// ->53428
27732 /* 53491*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
27767 /* 53567*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
27783 /* 53604*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
27818 /* 53680*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
27834 /* 53717*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
28176 /* 54438*/ OPC_SwitchOpcode /*2 cases */, 40, TARGET_VAL(ISD::AND),// ->54482
28221 /* 54528*/ OPC_SwitchOpcode /*2 cases */, 41, TARGET_VAL(ISD::AND),// ->54573
29355 /* 56647*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
29756 /* 57426*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
52295 /* 98632*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
53617 /*101255*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
53649 /*101328*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
54052 /*102133*/ OPC_SwitchOpcode /*3 cases */, 16, TARGET_VAL(ISD::AND),// ->102153
54092 /*102208*/ OPC_SwitchOpcode /*3 cases */, 17, TARGET_VAL(ISD::AND),// ->102229
gen/lib/Target/Lanai/LanaiGenDAGISel.inc 510 /* 852*/ /*SwitchOpcode*/ 108, TARGET_VAL(ISD::AND),// ->963
gen/lib/Target/MSP430/MSP430GenDAGISel.inc 62 /* 11*/ OPC_SwitchOpcode /*16 cases */, 32|128,12/*1568*/, TARGET_VAL(ISD::AND),// ->1584
2449 /* 5030*/ OPC_SwitchOpcode /*2 cases */, 47|128,2/*303*/, TARGET_VAL(ISD::AND),// ->5338
2775 /* 5632*/ /*SwitchOpcode*/ 120, TARGET_VAL(ISD::AND),// ->5755
2846 /* 5759*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
2924 /* 5902*/ /*SwitchOpcode*/ 105|128,7/*1001*/, TARGET_VAL(ISD::AND),// ->6907
gen/lib/Target/Mips/MipsGenDAGISel.inc 1382 /* 2481*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11037 /* 20651*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11236 /* 21023*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11437 /* 21397*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11555 /* 21606*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11676 /* 21818*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11754 /* 21955*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11839 /* 22101*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11891 /* 22190*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
12351 /* 23024*/ /*SwitchOpcode*/ 108|128,34/*4460*/, TARGET_VAL(ISD::AND),// ->27488
12488 /* 23281*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
12696 /* 23662*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
12901 /* 24044*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
13111 /* 24427*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
13318 /* 24811*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
13446 /* 25030*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
13570 /* 25249*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
13700 /* 25470*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
13827 /* 25692*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
13915 /* 25839*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
13999 /* 25986*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
14089 /* 26135*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
14179 /* 26290*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
14252 /* 26409*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
14309 /* 26507*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
14384 /* 26628*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
18453 /* 34558*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
18652 /* 34930*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
18853 /* 35304*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
18971 /* 35513*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
19092 /* 35725*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
19170 /* 35862*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
19255 /* 36008*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
19307 /* 36097*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
19669 /* 36753*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
20234 /* 37791*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
20788 /* 38809*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
27919 /* 52797*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
gen/lib/Target/Mips/MipsGenFastISel.inc 3409 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3955 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc58551 /*124319*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::AND),// ->124426
gen/lib/Target/PowerPC/PPCGenDAGISel.inc 3530 /* 7479*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
7185 /* 17245*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
19504 /* 49332*/ /*SwitchOpcode*/ 46, TARGET_VAL(ISD::AND),// ->49381
20407 /* 51684*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::AND),// ->51712
20499 /* 51831*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
20621 /* 52029*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::AND),// ->52057
20713 /* 52178*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
20760 /* 52295*/ /*SwitchOpcode*/ 30, TARGET_VAL(ISD::AND),// ->52328
22759 /* 56183*/ /*SwitchOpcode*/ 114|128,4/*626*/, TARGET_VAL(ISD::AND),// ->56813
23227 /* 57075*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
23244 /* 57101*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
23279 /* 57158*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
23319 /* 57225*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
23353 /* 57281*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
23380 /* 57328*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3233 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 57 /* 0*/ OPC_SwitchOpcode /*81 cases */, 12|128,5/*652*/, TARGET_VAL(ISD::AND),// ->657
6284 /* 11613*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
6376 /* 11780*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
6468 /* 11947*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
gen/lib/Target/Sparc/SparcGenDAGISel.inc 1511 /* 2714*/ /*SwitchOpcode*/ 77|128,1/*205*/, TARGET_VAL(ISD::AND),// ->2923
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc 1016 /* 1808*/ /*SwitchOpcode*/ 64|128,12/*1600*/, TARGET_VAL(ISD::AND),// ->3412
5633 /* 11004*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::AND),// ->11049
6169 /* 12025*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
6294 /* 12224*/ OPC_SwitchOpcode /*2 cases */, 15, TARGET_VAL(ISD::AND),// ->12243
6394 /* 12380*/ OPC_SwitchOpcode /*2 cases */, 15, TARGET_VAL(ISD::AND),// ->12399
6494 /* 12536*/ OPC_SwitchOpcode /*2 cases */, 15, TARGET_VAL(ISD::AND),// ->12555
6593 /* 12690*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
7646 /* 14790*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
7663 /* 14821*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
7754 /* 14964*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
7786 /* 15014*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
7818 /* 15064*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
7852 /* 15119*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
7945 /* 15268*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
7996 /* 15350*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8053 /* 15442*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8103 /* 15523*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8158 /* 15613*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8231 /* 15730*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8324 /* 15879*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8375 /* 15961*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8432 /* 16053*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8482 /* 16134*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8537 /* 16224*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8610 /* 16341*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8703 /* 16490*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8754 /* 16572*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8811 /* 16664*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8861 /* 16745*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8916 /* 16835*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
8989 /* 16952*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9082 /* 17101*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9133 /* 17183*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9190 /* 17275*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9240 /* 17356*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9290 /* 17440*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9398 /* 17624*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9432 /* 17681*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9466 /* 17738*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9504 /* 17802*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9628 /* 18012*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9680 /* 18103*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9735 /* 18201*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9780 /* 18283*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9822 /* 18363*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9907 /* 18509*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10031 /* 18719*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10083 /* 18810*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10138 /* 18908*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10183 /* 18990*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10225 /* 19070*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10310 /* 19216*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10434 /* 19426*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10486 /* 19517*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10541 /* 19615*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10586 /* 19697*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10628 /* 19777*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10713 /* 19923*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10837 /* 20133*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10889 /* 20224*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10944 /* 20322*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
10989 /* 20404*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11031 /* 20482*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11189 /* 20744*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11219 /* 20793*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11255 /* 20851*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11286 /* 20901*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11315 /* 20952*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11439 /* 21149*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11469 /* 21198*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11505 /* 21256*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11536 /* 21306*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11565 /* 21357*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11689 /* 21554*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11719 /* 21603*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11755 /* 21661*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11786 /* 21711*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11815 /* 21762*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11939 /* 21959*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
11969 /* 22008*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
12005 /* 22066*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
12036 /* 22116*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
12479 /* 22870*/ /*SwitchOpcode*/ 63|128,10/*1343*/, TARGET_VAL(ISD::AND),// ->24217
18015 /* 33452*/ OPC_SwitchOpcode /*2 cases */, 2|128,1/*130*/, TARGET_VAL(ISD::AND),// ->33587
18152 /* 33741*/ OPC_SwitchOpcode /*2 cases */, 2|128,1/*130*/, TARGET_VAL(ISD::AND),// ->33876
18289 /* 34030*/ OPC_SwitchOpcode /*2 cases */, 7|128,1/*135*/, TARGET_VAL(ISD::AND),// ->34170
18426 /* 34328*/ OPC_SwitchOpcode /*2 cases */, 112, TARGET_VAL(ISD::AND),// ->34444
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc 57 /* 0*/ OPC_SwitchOpcode /*93 cases */, 41|128,67/*8617*/, TARGET_VAL(ISD::AND),// ->8622
12777 /* 24600*/ /*SwitchOpcode*/ 32, TARGET_VAL(ISD::AND),// ->24635
16859 /* 32685*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
16865 /* 32695*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17013 /* 32936*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17042 /* 32982*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17076 /* 33038*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17104 /* 33083*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17129 /* 33126*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17247 /* 33310*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17276 /* 33356*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17310 /* 33412*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17338 /* 33457*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17363 /* 33500*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17481 /* 33684*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17510 /* 33730*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17544 /* 33786*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17572 /* 33831*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17597 /* 33874*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17715 /* 34058*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17744 /* 34104*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17777 /* 34157*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
17805 /* 34202*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1903 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc 555 /* 1049*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
579 /* 1098*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
603 /* 1147*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
627 /* 1196*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
875 /* 1723*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
899 /* 1772*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
923 /* 1821*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
947 /* 1870*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1195 /* 2397*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1219 /* 2446*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1243 /* 2495*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1267 /* 2544*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1515 /* 3071*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1539 /* 3120*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1563 /* 3169*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1587 /* 3218*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1900 /* 3887*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1924 /* 3936*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1948 /* 3985*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
1972 /* 4034*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
3460 /* 7404*/ /*SwitchOpcode*/ 103|128,5/*743*/, TARGET_VAL(ISD::AND),// ->8151
7488 /* 16056*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
7524 /* 16140*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
7563 /* 16228*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
7597 /* 16310*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
7616 /* 16354*/ /*SwitchOpcode*/ 56, TARGET_VAL(ISD::AND),// ->16413
7652 /* 16436*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
7733 /* 16617*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
9330 /* 20164*/ /*SwitchOpcode*/ 18|128,3/*402*/, TARGET_VAL(ISD::AND),// ->20570
9859 /* 21303*/ OPC_SwitchOpcode /*2 cases */, 86|128,2/*342*/, TARGET_VAL(ISD::AND),// ->21650
10348 /* 22267*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
18860 /* 37902*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
18885 /* 37959*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
18947 /* 38109*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
19138 /* 38514*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
19163 /* 38571*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
19221 /* 38714*/ /*SwitchOpcode*/ 35, TARGET_VAL(ISD::AND),// ->38752
19244 /* 38760*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
19449 /* 39199*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
19474 /* 39256*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
19561 /* 39464*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
20011 /* 40356*/ /*SwitchOpcode*/ 108|128,74|128,1/*25964*/, TARGET_VAL(ISD::AND),// ->66325
20336 /* 41121*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
20390 /* 41254*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
34149 /* 71008*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
34673 /* 72145*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
45143 /* 94484*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
45197 /* 94607*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
45628 /* 95546*/ OPC_SwitchOpcode /*2 cases */, 122|128,4/*634*/, TARGET_VAL(ISD::AND),// ->96185
45936 /* 96208*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
46035 /* 96406*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
46114 /* 96574*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
46199 /* 96750*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
46901 /* 98370*/ /*SwitchOpcode*/ 103|128,1/*231*/, TARGET_VAL(ISD::AND),// ->98605
47019 /* 98613*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
47564 /* 99711*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
47618 /* 99834*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
57006 /*120620*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
57087 /*120791*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
75996 /*160224*/ /*SwitchOpcode*/ 76|128,1/*204*/, TARGET_VAL(ISD::AND),// ->160432
79061 /*166152*/ /*SwitchOpcode*/ 29|128,1/*157*/, TARGET_VAL(ISD::AND),// ->166313
80816 /*169511*/ /*SwitchOpcode*/ 70|128,1/*198*/, TARGET_VAL(ISD::AND),// ->169713
84103 /*176226*/ /*SwitchOpcode*/ 25|128,1/*153*/, TARGET_VAL(ISD::AND),// ->176383
85850 /*179771*/ /*SwitchOpcode*/ 118|128,2/*374*/, TARGET_VAL(ISD::AND),// ->180149
89007 /*185808*/ /*SwitchOpcode*/ 14|128,2/*270*/, TARGET_VAL(ISD::AND),// ->186082
91448 /*190580*/ /*SwitchOpcode*/ 106|128,2/*362*/, TARGET_VAL(ISD::AND),// ->190946
95249 /*198330*/ /*SwitchOpcode*/ 10|128,2/*266*/, TARGET_VAL(ISD::AND),// ->198600
97980 /*203983*/ /*SwitchOpcode*/ 118|128,2/*374*/, TARGET_VAL(ISD::AND),// ->204361
102018 /*211790*/ /*SwitchOpcode*/ 14|128,2/*270*/, TARGET_VAL(ISD::AND),// ->212064
104771 /*217234*/ /*SwitchOpcode*/ 106|128,2/*362*/, TARGET_VAL(ISD::AND),// ->217600
109328 /*226612*/ /*SwitchOpcode*/ 10|128,2/*266*/, TARGET_VAL(ISD::AND),// ->226882
112446 /*233118*/ OPC_SwitchOpcode /*4 cases */, 16|128,3/*400*/, TARGET_VAL(ISD::AND),// ->233523
115859 /*239658*/ /*SwitchOpcode*/ 52|128,2/*308*/, TARGET_VAL(ISD::AND),// ->239970
123066 /*253828*/ /*SwitchOpcode*/ 124, TARGET_VAL(ISD::AND),// ->253955
124506 /*256396*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::AND),// ->256433
125720 /*258550*/ /*SwitchOpcode*/ 118, TARGET_VAL(ISD::AND),// ->258671
126925 /*260982*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::AND),// ->261019
128289 /*263698*/ /*SwitchOpcode*/ 0|128,5/*640*/, TARGET_VAL(ISD::AND),// ->264342
133934 /*274703*/ /*SwitchOpcode*/ 108|128,4/*620*/, TARGET_VAL(ISD::AND),// ->275327
140440 /*288316*/ /*SwitchOpcode*/ 36|128,1/*164*/, TARGET_VAL(ISD::AND),// ->288484
142428 /*291835*/ /*SwitchOpcode*/ 28|128,1/*156*/, TARGET_VAL(ISD::AND),// ->291995
144464 /*295906*/ /*SwitchOpcode*/ 64, TARGET_VAL(ISD::AND),// ->295973
145708 /*298108*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
146596 /*299632*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::AND),// ->299696
147618 /*301685*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::AND),// ->301706
148597 /*303632*/ /*SwitchOpcode*/ 87|128,2/*343*/, TARGET_VAL(ISD::AND),// ->303979
152006 /*309976*/ /*SwitchOpcode*/ 77|128,2/*333*/, TARGET_VAL(ISD::AND),// ->310313
155858 /*317590*/ /*SwitchOpcode*/ 84, TARGET_VAL(ISD::AND),// ->317677
157190 /*319868*/ /*SwitchOpcode*/ 80, TARGET_VAL(ISD::AND),// ->319951
158648 /*322662*/ /*SwitchOpcode*/ 124, TARGET_VAL(ISD::AND),// ->322789
159586 /*324322*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::AND),// ->324359
160484 /*325902*/ /*SwitchOpcode*/ 118, TARGET_VAL(ISD::AND),// ->326023
161312 /*327564*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::AND),// ->327601
162231 /*329404*/ /*SwitchOpcode*/ 0|128,5/*640*/, TARGET_VAL(ISD::AND),// ->330048
167506 /*339687*/ /*SwitchOpcode*/ 108|128,4/*620*/, TARGET_VAL(ISD::AND),// ->340311
173834 /*352945*/ OPC_SwitchOpcode /*4 cases */, 36|128,1/*164*/, TARGET_VAL(ISD::AND),// ->353114
175291 /*355547*/ OPC_SwitchOpcode /*4 cases */, 28|128,1/*156*/, TARGET_VAL(ISD::AND),// ->355708
176882 /*358799*/ OPC_SwitchOpcode /*4 cases */, 64, TARGET_VAL(ISD::AND),// ->358867
177392 /*359665*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::AND),// ->359687
177873 /*360470*/ OPC_SwitchOpcode /*4 cases */, 61, TARGET_VAL(ISD::AND),// ->360535
178335 /*361361*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::AND),// ->361382
179003 /*362657*/ OPC_SwitchOpcode /*4 cases */, 34|128,5/*674*/, TARGET_VAL(ISD::AND),// ->363336
185069 /*374465*/ OPC_SwitchOpcode /*4 cases */, 84, TARGET_VAL(ISD::AND),// ->374553
185846 /*375793*/ OPC_SwitchOpcode /*4 cases */, 80, TARGET_VAL(ISD::AND),// ->375877
206668 /*418553*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
229117 /*467593*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
229203 /*467783*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
229280 /*467960*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
229337 /*468080*/ /*SwitchOpcode*/ 45|128,2/*301*/, TARGET_VAL(ISD::AND),// ->468385
gen/lib/Target/X86/X86GenFastISel.inc13512 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
14111 case ISD::AND: return fastEmit_ISD_AND_ri(VT, RetVT, Op0, Op0IsKill, imm1);
14243 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_i64immSExt32(VT, RetVT, Op0, Op0IsKill, imm1);
14348 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_i16immSExt8(VT, RetVT, Op0, Op0IsKill, imm1);
14452 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_i32immSExt8(VT, RetVT, Op0, Op0IsKill, imm1);
14556 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_i64immSExt8(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/XCore/XCoreGenDAGISel.inc 1263 /* 2065*/ /*SwitchOpcode*/ 91, TARGET_VAL(ISD::AND),// ->2159
include/llvm/CodeGen/TargetLowering.h 2273 case ISD::AND:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1528 case ISD::AND: return visitAND(N);
1648 case ISD::AND:
1950 (BinOpcode == ISD::AND || BinOpcode == ISD::OR) &&
2017 SetCC.getOperand(0).getOpcode() != ISD::AND ||
2368 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) {
2405 if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1)))
2475 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
2702 return CombineTo(N, DAG.getNode(ISD::AND, DL, VT, CarryExt,
3129 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
3906 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
3913 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
4254 assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR ||
4319 HandOpcode == ISD::SRA || HandOpcode == ISD::AND) &&
4476 SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);
4529 SDValue And = DAG.getNode(ISD::AND, DL, OpVT, Add, MaskC);
4627 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) &&
4647 SDValue And = DAG.getNode(ISD::AND, SL, HalfVT, Shift, NewMask);
4828 case ISD::AND:
4885 SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode),
4889 if (And.getOpcode() == ISD ::AND)
4901 SDValue And = DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(),
4910 SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0),
4913 if (And.getOpcode() == ISD ::AND)
4933 assert(N->getOpcode() == ISD::AND);
4985 assert(And->getOpcode() == ISD::AND && "Expected an 'and' op");
5028 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, Mask);
5069 return DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, N0C, N1C);
5073 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
5087 if (SDValue RAND = reassociateOps(ISD::AND, SDLoc(N), N0, N1, N->getFlags()))
5339 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
5341 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
5343 if (N0.getOpcode() == ISD::AND) {
5356 if (N1.getOpcode() == ISD::AND) {
5382 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
5393 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
5448 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
5453 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL)
5458 if (Opc == ISD::AND)
5460 else if (Opc0 == ISD::AND)
5474 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) {
5484 if (Opc == ISD::AND) {
5616 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
5616 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
5634 return DAG.getNode(ISD::AND, DL, VT, X,
5642 if (N0.getOpcode() == ISD::AND &&
5643 N1.getOpcode() == ISD::AND &&
5649 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), X);
5659 if (N0.getOpcode() == ISD::AND) {
5805 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
5811 return DAG.getNode(ISD::AND, SDLoc(N), VT, COR, IOR);
5846 if (Op.getOpcode() == ISD::AND &&
6038 if (Neg.getOpcode() == ISD::AND && isPowerOf2_64(EltSize)) {
6060 if (MaskLoBits && Pos.getOpcode() == ISD::AND) {
6231 Mask = DAG.getNode(ISD::AND, DL, VT, Mask,
6236 Mask = DAG.getNode(ISD::AND, DL, VT, Mask,
6240 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, Mask);
6800 if (And.getOpcode() != ISD::AND || !And.hasOneUse())
6843 SDValue LHS = DAG.getNode(ISD::AND, DL, VT, NotX, M);
6846 return DAG.getNode(ISD::AND, DL, VT, NotLHS, RHS);
6849 SDValue LHS = DAG.getNode(ISD::AND, DL, VT, X, M);
6851 SDValue RHS = DAG.getNode(ISD::AND, DL, VT, Y, NotM);
6935 (N0Opcode == ISD::OR || N0Opcode == ISD::AND)) {
6938 unsigned NewOpcode = N0Opcode == ISD::AND ? ISD::OR : ISD::AND;
6938 unsigned NewOpcode = N0Opcode == ISD::AND ? ISD::OR : ISD::AND;
6947 (N0Opcode == ISD::OR || N0Opcode == ISD::AND)) {
6950 unsigned NewOpcode = N0Opcode == ISD::AND ? ISD::OR : ISD::AND;
6950 unsigned NewOpcode = N0Opcode == ISD::AND ? ISD::OR : ISD::AND;
6968 if (N0Opcode == ISD::AND && N0.hasOneUse() && N0->getOperand(1) == N1) {
6972 return DAG.getNode(ISD::AND, DL, VT, NotX, N1);
7068 if (LogicOpcode != ISD::AND && LogicOpcode != ISD::OR &&
7158 case ISD::AND:
7202 assert(N->getOperand(0).getOpcode() == ISD::AND);
7207 TLI.isTypeDesirableForOp(ISD::AND, TruncVT)) {
7216 return DAG.getNode(ISD::AND, DL, TruncVT, Trunc00, Trunc01);
7253 N1.getOperand(0).getOpcode() == ISD::AND) {
7300 if (N0.getOpcode() == ISD::AND) {
7310 return DAG.getNode(ISD::AND, SDLoc(N), VT, N00, C);
7334 N1.getOperand(0).getOpcode() == ISD::AND) {
7484 return DAG.getNode(ISD::AND, DL, VT, Shift,
7496 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), HiBitsMask);
7677 N1.getOperand(0).getOpcode() == ISD::AND) {
7811 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), Mask);
7833 return DAG.getNode(ISD::AND, DL, VT,
7885 N1.getOperand(0).getOpcode() == ISD::AND) {
8210 return DAG.getNode(ISD::AND, DL, VT, Sra, C1);
8347 return DAG.getNode(ISD::AND, DL, VT, NOTNode, N2);
8358 return DAG.getNode(ISD::AND, DL, VT, N0, N1);
8377 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) {
8411 SDValue And = DAG.getNode(ISD::AND, DL, N0.getValueType(), N0, N1_0);
9165 if (!(N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
9190 if (N1.getOpcode() == ISD::SHL && N0.getOpcode() != ISD::AND)
9496 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
9749 if (!LegalOperations || (TLI.isOperationLegal(ISD::AND, SrcVT) &&
9761 if (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) {
9774 if (N0.getOpcode() == ISD::AND &&
9785 return DAG.getNode(ISD::AND, DL, VT,
9809 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
9821 if (N0.getOpcode() == ISD::AND) {
9896 return DAG.getNode(ISD::AND, DL, VT, VSetCC, VecOnes);
9906 return DAG.getNode(ISD::AND, DL, VT, DAG.getSExtOrTrunc(VsetCC, DL, VT),
9990 if (N0.getOpcode() == ISD::AND &&
10000 return DAG.getNode(ISD::AND, DL, VT,
10203 } else if (Opc == ISD::AND) {
10258 if (Mask->getOpcode() == ISD::AND &&
10829 case ISD::AND:
10915 case ISD::AND:
11056 FlipBit = DAG.getNode(ISD::AND, SDLoc(N0), MVT::i64, Hi, SignBit);
11069 return DAG.getNode(ISD::AND, DL, VT,
11125 DAG.getNode(ISD::AND, SDLoc(XorResult64), MVT::i64, XorResult64,
11134 X = DAG.getNode(ISD::AND, SDLoc(X), VT,
11139 Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT,
13286 Int = DAG.getNode(ISD::AND, DL, IntVT, Int,
13354 if (Op0.getOpcode() == ISD::AND && Op1.getOpcode() == ISD::Constant) {
13994 auto Val = DAG.getNode(ISD::AND, SDLoc(LD), LDType, ST->getValue(), Mask);
14708 if (V->getOpcode() != ISD::AND ||
14874 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
14891 if (Opc == ISD::AND)
14919 if (Opc == ISD::AND)
18150 if (BOpcode != ISD::AND && BOpcode != ISD::OR && BOpcode != ISD::XOR)
19400 if (N0->getOpcode() == ISD::AND) {
19446 assert(N->getOpcode() == ISD::AND && "Unexpected opcode!");
19952 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
19967 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
20068 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
20089 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
lib/CodeGen/SelectionDAG/FastISel.cpp 597 if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
644 ISDOpcode = ISD::AND;
1829 return selectBinaryOp(I, ISD::AND);
2242 return fastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1513 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue,
1532 SDValue ClearedSign = DAG.getNode(ISD::AND, DL, MagVT, MagAsInt.IntValue,
1574 SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, ValueAsInt.IntValue,
1603 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1675 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1697 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
2561 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi4, dl, VT));
2562 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo4, dl, VT));
2568 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi2, dl, VT));
2569 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo2, dl, VT));
2575 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi1, dl, VT));
2576 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo1, dl, VT));
2594 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
2616 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2618 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2631 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2633 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2635 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2637 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2639 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2641 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2866 SDValue And = DAG.getNode(ISD::AND, dl, VT, Node->getOperand(0), One);
3375 Overflow2 = DAG.getNode(ISD::AND, dl, SetCCType, Overflow2,
3492 (Tmp2.getOpcode() == ISD::AND &&
3497 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
4227 case ISD::AND:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 174 return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask);
274 SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit);
300 LHS = DAG.getNode(ISD::AND, dl, LVT, LHS, Mask);
1698 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1703 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 126 case ISD::AND:
1754 case ISD::AND:
1939 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
2201 OVF = DAG.getNode(ISD::AND, dl, OvfVT, DAG.getConstant(1, dl, OvfVT), OVF);
2802 SDValue LLL = DAG.getNode(ISD::AND, dl, NVT, LL, Mask);
2803 SDValue RLL = DAG.getNode(ISD::AND, dl, NVT, RL, Mask);
2806 SDValue TL = DAG.getNode(ISD::AND, dl, NVT, T, Mask);
2821 SDValue UL = DAG.getNode(ISD::AND, dl, NVT, U, Mask);
3039 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLUGT));
3045 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLULT));
3052 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLNeg));
3058 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLPos));
3119 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3384 SDValue Overflow = DAG.getNode(ISD::AND, dl, BitVT,
3657 NewLHS = DAG.getNode(ISD::AND, dl,
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 375 case ISD::AND:
721 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
906 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
936 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
937 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
1109 TLI.isOperationLegalOrCustomOrPromote(ISD::AND, ByteVT) &&
1124 !TLI.isOperationLegalOrCustomOrPromote(ISD::AND, VT) ||
1150 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
1173 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
1174 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
1234 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 109 case ISD::AND:
491 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
945 case ISD::AND:
2126 case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break;
2733 case ISD::AND:
3804 case ISD::AND:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 1139 return getNode(ISD::AND, DL, Op.getValueType(), Op,
1914 getNode(ISD::AND, dl, VAList.getValueType(), VAList,
2177 case ISD::AND: {
2308 case ISD::AND: {
2687 case ISD::AND:
3576 case ISD::AND:
4700 case ISD::AND: return std::make_pair(C1 & C2, true);
5077 case ISD::AND:
5406 case ISD::AND:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 2711 SDValue AndOp = DAG.getNode(ISD::AND, dl,
3987 DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize,
4865 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
4879 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
6873 setValue(&I, DAG.getNode(ISD::AND, getCurSDLoc(), DestVT, Ptr,
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h 686 void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 236 case ISD::AND: return "and";
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 2577 if (N->getOpcode() != ISD::AND) return false;
lib/CodeGen/SelectionDAG/TargetLowering.cpp 482 case ISD::AND:
658 case ISD::AND: {
1007 case ISD::AND: {
1188 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, ANDC));
2518 case ISD::AND: {
2785 if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND)
2785 if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND)
2789 if (N0.getOpcode() != ISD::AND || !OpVT.isInteger() ||
2830 SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, NotX, Y);
2982 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
3000 SDValue T1 = DAG.getNode(ISD::AND, DL, VT, T0, C);
3123 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add);
3137 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add);
3140 unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR;
3156 } else if (N0->getOpcode() == ISD::AND) {
3239 N0.getOpcode() == ISD::AND && C1 == 0 &&
3285 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
3366 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
3399 (N0.getOpcode() == ISD::AND &&
3415 assert(N0.getOpcode() == ISD::AND &&
3418 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
3442 if (Op0.getOpcode() == ISD::AND &&
3447 Op0 = DAG.getNode(ISD::AND, dl, VT,
3451 Op0 = DAG.getNode(ISD::AND, dl, VT,
3616 N0.getOpcode() == ISD::AND) {
3647 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
3894 N0 = DAG.getNode(ISD::AND, dl, OpVT, N1, Temp);
3901 N0 = DAG.getNode(ISD::AND, dl, OpVT, N0, Temp);
4735 T = DAG.getNode(ISD::AND, dl, VT, T, ShiftMask);
5297 !isOperationLegalOrCustom(ISD::AND, VT) ||
5316 SDValue Masked = DAG.getNode(ISD::AND, DL, VT, N, IntMax);
5812 ShAmt = DAG.getNode(ISD::AND, DL, ShVT, Z, Mask);
5858 !isOperationLegalOrCustomOrPromote(ISD::AND, VT)))
5871 SDValue And0 = DAG.getNode(ISD::AND, DL, ShVT, Op1, BitWidthMinusOneC);
5872 SDValue And1 = DAG.getNode(ISD::AND, DL, ShVT, NegOp1, BitWidthMinusOneC);
5914 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
5919 DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
5924 DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
6054 !isOperationLegalOrCustomOrPromote(ISD::AND, SrcVT)))
6064 SDValue And = DAG.getNode(ISD::AND, dl, SrcVT, Src, AndConst);
6091 !isOperationLegalOrCustomOrPromote(ISD::AND, SrcVT)))
6105 SDValue Lo = DAG.getNode(ISD::AND, dl, SrcVT, Src, LoMask);
6177 !isOperationLegalOrCustomOrPromote(ISD::AND, VT)))
6193 DAG.getNode(ISD::AND, dl, VT,
6198 Op = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
6199 DAG.getNode(ISD::AND, dl, VT,
6204 Op = DAG.getNode(ISD::AND, dl, VT,
6303 !isOperationLegalOrCustomOrPromote(ISD::AND, VT) ||
6312 ISD::AND, dl, VT, DAG.getNOT(dl, Op, VT),
6785 return DAG.getNode(ISD::AND, dl, IdxVT, Idx,
6945 return DAG.getNode(ISD::AND, dl, VT, SumDiff, Not);
7325 case ISD::VECREDUCE_AND: BaseOpcode = ISD::AND; break;
lib/CodeGen/TargetLoweringBase.cpp 1607 case And: return ISD::AND;
lib/Target/AArch64/AArch64FastISel.cpp 1694 static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR),
1694 static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR),
1711 unsigned Idx = ISDOpc - ISD::AND;
1718 Opc = OpcTable[ISDOpc - ISD::AND][1];
1730 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) {
1741 static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR),
1741 static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR),
1762 Opc = OpcTable[ISDOpc - ISD::AND][0];
1766 Opc = OpcTable[ISDOpc - ISD::AND][1];
1782 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm);
1961 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 481 } else if (N.getOpcode() == ISD::AND) {
1539 assert(N->getOpcode() == ISD::AND &&
1559 if (!isOpcWithIntImmediate(N, ISD::AND, AndImm))
1680 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, AndMask))
1808 case ISD::AND:
2151 if (isOpcWithIntImmediate(Op.getNode(), ISD::AND, AndImm)) {
2216 !isOpcWithIntImmediate(And.getNode(), ISD::AND, MaskImm))
2374 if (isOpcWithIntImmediate(OrOpd1, ISD::AND, Imm) &&
2399 isOpcWithIntImmediate(And0.getNode(), ISD::AND, Mask0Imm) &&
2400 isOpcWithIntImmediate(And1.getNode(), ISD::AND, Mask1Imm) &&
2464 if (N->getOpcode() != ISD::AND)
2570 if (!isOpcWithIntImmediate(ShiftAmt.getNode(), ISD::AND, MaskImm))
2913 case ISD::AND:
lib/Target/AArch64/AArch64ISelLowering.cpp 584 setTargetDAGCombine(ISD::AND);
1033 case ISD::AND:
1633 } else if (LHS.getOpcode() == ISD::AND && isNullConstant(RHS) &&
1764 if (Opcode == ISD::AND || Opcode == ISD::OR) {
1792 assert(Opcode == ISD::AND && "Must be OR or AND");
1898 assert(Opcode == ISD::AND && "Valid conjunction/disjunction tree");
1941 if (V.getOpcode() == ISD::AND)
2746 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
4739 if (LHS.getOpcode() == ISD::AND &&
4755 if (LHS.getOpcode() == ISD::AND &&
4766 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
4776 LHS.getOpcode() != ISD::AND && ProduceNonFlagSettingCondBr) {
5462 VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
7373 if (And.getOpcode() != ISD::AND)
8331 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
8346 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
9223 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
9489 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
9512 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
9778 if (N0.getOpcode() != ISD::AND)
9782 if (N1.getOpcode() != ISD::AND)
10447 if (AndN.getOpcode() != ISD::AND)
11338 if (AndNode->getOpcode() != ISD::AND)
11496 case ISD::AND:
11739 case ISD::AND:
lib/Target/AArch64/AArch64TargetTransformInfo.cpp 565 case ISD::AND:
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 874 case ISD::AND:
1937 case ISD::AND:
1960 if (N->getOperand(0).getOpcode() == ISD::AND) {
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 363 setOperationAction(ISD::AND, VT, Expand);
1625 Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask);
1626 Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask);
1818 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, One);
1914 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
2051 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2094 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
2106 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
2218 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2227 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2277 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2371 SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0OrHi0, Hi0orLo0);
2438 SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64,
2442 SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U,
2458 SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One);
2608 E = DAG.getNode(ISD::AND, DL, MVT::i32, E,
2617 M = DAG.getNode(ISD::AND, DL, MVT::i32, M,
2620 SDValue MaskedSig = DAG.getNode(ISD::AND, DL, MVT::i32, UH,
2653 SDValue VLow3 = DAG.getNode(ISD::AND, DL, MVT::i32, V,
2672 Sign = DAG.getNode(ISD::AND, DL, MVT::i32, Sign,
3130 if (LHS.getOpcode() == ISD::AND) {
3135 ISD::AND, SL, VT,
3849 SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src,
4169 return DAG.getNode(ISD::AND, SL, VT, V,
lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp 372 case ISD::AND:
lib/Target/AMDGPU/R600ISelLowering.cpp 1172 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1184 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1211 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1287 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, PtrVT, Ptr,
1296 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1403 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1413 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
lib/Target/AMDGPU/SIISelLowering.cpp 549 setOperationAction(ISD::AND, MVT::v2i16, Promote);
550 AddPromotedToType(ISD::AND, MVT::v2i16, MVT::i32);
716 setTargetDAGCombine(ISD::AND);
1378 case ISD::AND:
4362 SDValue Op = DAG.getNode(ISD::AND, SL, MVT::i32,
4853 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal);
4854 SDValue RHS = DAG.getNode(ISD::AND, SL, IntVT,
8114 return (Opc == ISD::AND && (Val == 0 || Val == 0xffffffff)) ||
8154 case ISD::AND:
8200 case ISD::AND:
8242 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::AND, LHS, CRHS))
9995 case ISD::AND:
lib/Target/ARC/ARCISelLowering.cpp 96 setOperationAction(ISD::AND, MVT::i32, Legal);
lib/Target/ARM/ARMISelDAGToDAG.cpp 370 if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
371 if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
420 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
2644 if (N->getOpcode() == ISD::AND) {
2645 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2725 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, And_imm) &&
2861 And->getOpcode() != ISD::AND)
3109 case ISD::AND: {
lib/Target/ARM/ARMISelLowering.cpp 192 setOperationAction(ISD::AND, VT, Promote);
193 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
360 setOperationAction(ISD::AND, MVT::v2i64, Legal);
1418 setTargetDAGCombine(ISD::AND);
4249 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4602 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
4911 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
5146 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5148 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5160 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
5161 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
5487 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
5488 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
5509 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
5511 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
5521 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
5885 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
5898 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
6198 SDValue Merged = DAG.getNode(ISD::AND, dl, SplitVT, Cmp, Reversed);
6292 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
11598 if (N1->getOpcode() != ISD::ADD && N1->getOpcode() != ISD::AND &&
11671 case ISD::AND:
11692 N->getOpcode() != ISD::XOR && N->getOpcode() != ISD::AND)
12175 } else if (N1.getOpcode() == ISD::AND) {
12310 SDValue And = DCI.DAG.getNode(ISD::AND, SDLoc(N), VT, NewN0, NewN1);
12360 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
12366 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
12405 if (N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
12516 if (N1.getOpcode() == ISD::AND) {
13760 N->getOperand(0)->getOpcode() == ISD::AND &&
13969 if (And->getOpcode() != ISD::AND)
14218 if (CC == ARMCC::NE && LHS.getOpcode() == ISD::AND && LHS->hasOneUse() &&
14428 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
15481 if (Op.getOpcode() != ISD::AND)
15522 SDValue NewOp = TLO.DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), NewC);
16076 SP = DAG.getNode(ISD::AND, DL, MVT::i32, SP.getValue(0),
lib/Target/BPF/BPFISelDAGToDAG.cpp 334 else if (Opcode == ISD::AND)
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 945 case ISD::AND:
1102 if (T0.getOpcode() != ISD::AND)
1521 case ISD::AND: {
lib/Target/Hexagon/HexagonISelLowering.cpp 747 SDValue T = DAG.getNode(ISD::AND, dl, RegVT,
1424 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1489 setOperationAction(ISD::AND, NativeVT, Legal);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 76 setOperationAction(ISD::AND, T, Legal);
153 setOperationAction(ISD::AND, T, Custom);
179 setOperationAction(ISD::AND, BoolW, Custom);
192 setOperationAction(ISD::AND, BoolV, Legal);
307 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask});
529 return DAG.getNode(ISD::AND, dl, ByteTy, S, M);
712 SDValue MaskV = DAG.getNode(ISD::AND, dl, MVT::i32,
1259 SDValue A = DAG.getNode(ISD::AND, dl, ResTy,
1538 case ISD::AND:
lib/Target/Lanai/LanaiAluCode.h 128 case ISD::AND:
lib/Target/Lanai/LanaiISelLowering.cpp 143 setTargetDAGCombine(ISD::AND);
1479 case ISD::AND:
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp 429 case ISD::AND:
lib/Target/MSP430/MSP430ISelLowering.cpp 1141 (LHS.getOpcode() == ISD::AND ||
1143 LHS.getOperand(0).getOpcode() == ISD::AND))) {
1192 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
lib/Target/Mips/MipsFastISel.cpp 304 case ISD::AND:
875 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
lib/Target/Mips/MipsISelLowering.cpp 503 setTargetDAGCombine(ISD::AND);
879 if (And0.getOpcode() != ISD::AND)
887 if (And1.getOpcode() == ISD::AND &&
925 bool isConstCase = And1.getOpcode() != ISD::AND;
926 if (And1.getOpcode() == ISD::AND) {
1131 if (FirstOperandOpc != ISD::AND)
1168 case ISD::AND:
2173 ISD::AND, DL, VAList.getValueType(), VAList,
2473 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2512 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
lib/Target/Mips/MipsSEISelLowering.cpp 163 setTargetDAGCombine(ISD::AND);
333 setOperationAction(ISD::AND, Ty, Legal);
610 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
610 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
1030 case ISD::AND:
1412 DAG.getNode(ISD::AND, DL, ViaVecTy, Result, One));
1517 return DAG.getNode(ISD::AND, DL, ResTy, Vec, SplatVec);
1526 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1537 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1592 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1595 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 486 case ISD::AND:
3385 if (N->getOpcode() == ISD::AND) {
3442 if (LHS->getOpcode() == ISD::AND) {
lib/Target/NVPTX/NVPTXISelLowering.cpp 518 setTargetDAGCombine(ISD::AND);
2107 SDValue Sign = DAG.getNode(ISD::AND, SL, MVT::i32, Bitcast,
4767 case ISD::AND:
lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp 130 case ISD::AND:
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 734 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
734 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
745 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
760 if (Op1Opc == ISD::AND) {
1269 case ISD::AND:
2516 case ISD::AND:
2526 return Opc == ISD::AND || Opc == ISD::OR || Opc == ISD::XOR;
2701 case ISD::AND: NewOpc = PPC::AND8; break;
3636 case ISD::AND:
3662 case ISD::AND:
4568 case ISD::AND: {
4757 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
4771 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
5346 if (Op.getOpcode() == ISD::AND) {
5437 Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
5446 Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
lib/Target/PowerPC/PPCISelLowering.cpp 607 setOperationAction(ISD::AND , VT, Promote);
608 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
691 setOperationAction(ISD::AND , MVT::v4i32, Legal);
1026 setOperationAction(ISD::AND , MVT::v4i1, Legal);
3047 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
7783 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
7788 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
8000 DAG.getNode(ISD::AND, dl, MVT::i32,
8004 DAG.getNode(ISD::AND, dl, MVT::i32,
9509 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
9591 DAG.getNode(ISD::AND, dl, MVT::i32, CmpOp,
12077 if (N->getOperand(0).getOpcode() != ISD::AND &&
12089 N->getOperand(1).getOpcode() != ISD::AND &&
12142 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
12323 if (N->getOperand(0).getOpcode() != ISD::AND &&
12355 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
12563 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
13998 if (LHS.getOpcode() == ISD::AND &&
15124 N1->getOpcode() == ISD::AND)
lib/Target/RISCV/RISCVISelDAGToDAG.cpp 90 if (Node->getOpcode() == ISD::AND &&
lib/Target/RISCV/RISCVISelLowering.cpp 968 SDValue NewHi = DAG.getNode(ISD::AND, DL, MVT::i32, Hi,
1014 DAG.getNode(ISD::AND, DL, MVT::i64, NewFMV,
lib/Target/Sparc/SparcISelLowering.cpp 2248 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2281 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2288 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 722 if (Op.getOpcode() != ISD::AND)
783 case ISD::AND: {
970 if (Count == 1 && N->getOpcode() != ISD::AND)
1005 SDValue New = CurDAG->getNode(ISD::AND, DL, VT, In, Mask);
1494 if (ChildOpcode == ISD::AND || ChildOpcode == ISD::OR ||
1513 case ISD::AND:
1866 Result = CurDAG->getNode(ISD::AND, DL, VT, Result,
lib/Target/SystemZ/SystemZISelLowering.cpp 345 setOperationAction(ISD::AND, VT, Legal);
2122 Opcode0 == ISD::AND &&
2351 if (C.Op0.getOpcode() == ISD::AND) {
2432 if (C.Op0.getOpcode() != ISD::AND)
3260 DAG.getNode(ISD::AND, DL, MVT::i64, Result,
3318 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
3319 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
3417 if (HighOp.getOpcode() == ISD::AND &&
3607 Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp,
3694 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3810 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp 202 Char = DAG.getNode(ISD::AND, DL, MVT::i32, Char,
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 1497 ISD::AND, // mask opcode
lib/Target/X86/X86FastISel.cpp 3284 fastEmit_ri(VT, VT, ISD::AND, ResultReg, hasTrivialKill(PrevVal), 1);
lib/Target/X86/X86ISelDAGToDAG.cpp 441 assert(N->getOpcode() == ISD::AND && "Unexpected opcode");
564 if (N->getOpcode() == ISD::AND)
598 case ISD::AND:
622 if (U->getOpcode() == ISD::AND &&
630 if (U->getOpcode() == ISD::AND &&
672 if (U->getOpcode() == ISD::AND) {
797 SDValue Res = CurDAG->getNode(ISD::AND, SDLoc(N), N->getValueType(0),
923 case X86ISD::FAND: Opc = ISD::AND; break;
1585 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
1656 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
1822 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, NewSRL, NewMask);
1952 if (And.getOpcode() != ISD::AND) break;
2092 case ISD::AND: {
3189 (Node->getOpcode() == ISD::AND || Node->getOpcode() == ISD::SRL) &&
3337 if (Node->getOpcode() == ISD::AND) {
3697 NewShiftAmt = CurDAG->getNode(ISD::AND, DL, MVT::i8, NewShiftAmt,
3765 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
3771 if (Opcode == ISD::AND) {
3785 if (Opcode != ISD::AND) {
3803 if (Opcode == ISD::AND) {
3945 SDValue NewAnd = CurDAG->getNode(ISD::AND, SDLoc(And), VT, And0, NewMask);
4148 if (N0Temp.getOpcode() == ISD::AND && N0Temp.hasOneUse()) {
4319 if (N1.getOpcode() == ISD::AND)
4322 if (N0.getOpcode() != ISD::AND ||
4478 case ISD::AND:
4561 case ISD::AND: ROpc = X86::AND8rr; MOpc = X86::AND8rm; break;
4571 case ISD::AND: ROpc = X86::AND16rr; MOpc = X86::AND16rm; break;
4581 case ISD::AND: ROpc = X86::AND32rr; MOpc = X86::AND32rm; break;
4591 case ISD::AND: ROpc = X86::AND64rr; MOpc = X86::AND64rm; break;
4986 if (N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
5005 if (N0.getOpcode() == ISD::AND &&
lib/Target/X86/X86ISelLowering.cpp 1850 setTargetDAGCombine(ISD::AND);
4572 case ISD::AND:
6881 case ISD::AND:
8538 Cond = DAG.getNode(ISD::AND, dl, MVT::i8, Cond,
9210 case ISD::AND:
10941 SDValue And = DAG.getNode(ISD::AND, DL, LogicVT, V, VMask);
10965 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
14409 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
14411 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
14449 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
18241 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
18259 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
18319 Amt = DAG.getNode(ISD::AND, DL, Amt.getValueType(), Amt,
18669 SDValue LO = DAG.getNode(ISD::AND, DL, MVT::v4i32, N0, HalfWordMask);
18752 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
19502 In = DAG.getNode(ISD::AND, DL, InVT, In, DAG.getConstant(255, DL, InVT));
19881 Res = DAG.getNode(ISD::AND, dl, VT, Res, DAG.getConstant(1, dl, VT));
20068 case ISD::AND:
20095 case ISD::AND: Opcode = X86ISD::AND; break;
20366 assert(And.getOpcode() == ISD::AND && "Expected AND node!");
20744 if (BC0.getOpcode() == ISD::AND) {
20759 if (Cond == ISD::SETEQ && Op0.getOpcode() == ISD::AND &&
20890 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
20914 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
20979 if (KTestable && Op0.getOpcode() == ISD::AND && Op0.hasOneUse()) {
21008 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && isNullConstant(Op1) &&
21364 Cmp.getOperand(0).getOpcode() == ISD::AND &&
21390 Neg = DAG.getNode(ISD::AND, DL, VT,
21397 SDValue And = DAG.getNode(ISD::AND, DL, VT, Mask, Src1); // Mask & z
21404 if (Cond.getOpcode() == ISD::AND &&
21445 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
21946 if (Opc != ISD::OR && Opc != ISD::AND)
22002 if (Cond.getOpcode() == ISD::AND &&
22164 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
22227 Result = DAG.getNode(ISD::AND, dl, VT, Result,
22260 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
22669 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
23158 SetCC = DAG.getNode(ISD::AND, dl, MVT::i8, SetCC, SetNP);
24566 DAG.getNode(ISD::AND, DL, MVT::i16,
24571 DAG.getNode(ISD::AND, DL, MVT::i16,
24576 DAG.getNode(ISD::AND, DL, MVT::i16,
24700 Lo = DAG.getNode(ISD::AND, DL, CurrVT, Lo, HiZ);
24733 R1 = DAG.getNode(ISD::AND, DL, NextVT, ResNext, R1);
24913 return DAG.getNode(ISD::AND, dl, VT, X, DAG.getNOT(dl, Y, VT));
25024 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
25081 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
25082 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
25229 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
25231 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
25584 return DAG.getNode(ISD::AND, dl, VT, SHL, DAG.getConstant(Mask, dl, VT));
25592 return DAG.getNode(ISD::AND, dl, VT, SRL,
25660 Res = DAG.getNode(ISD::AND, dl, VT, Res, BitMask);
26382 Amt = DAG.getNode(ISD::AND, DL, VT, Amt,
26937 SDValue LoNibbles = DAG.getNode(ISD::AND, DL, VT, Op, M0F);
27076 SDValue Lo = DAG.getNode(ISD::AND, DL, VT, In, NibbleMask);
31428 if (Op.getOpcode() != ISD::AND)
31477 SDValue NewOp = TLO.DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), NewC);
32649 FloatDomain ? unsigned(X86ISD::FAND) : unsigned(ISD::AND);
35182 case ISD::AND:
35197 case ISD::AND:
35351 if (Op.getOpcode() != ISD::AND &&
35660 case ISD::AND: FPOpcode = X86ISD::FAND; break;
35837 SDValue Match = DAG.matchBinOpReduction(Extract, BinOp, {ISD::OR, ISD::AND});
35925 Result = DAG.getNode(ISD::AND, DL, CmpVT, Result, Mask);
36501 SDValue Res = DAG.getNode(ISD::AND, dl, BCVT, BC, Mask);
36610 SDValue And = DAG.getNode(ISD::AND, DL, CondVT, Cond, CastLHS);
36993 if (AndNode.getOpcode() == ISD::AND && CC == ISD::SETEQ &&
37392 SetCC.getOpcode() == ISD::AND) {
37393 if (SetCC.getOpcode() == ISD::AND) {
37487 case ISD::AND:
37521 (Carry.getOpcode() == ISD::AND &&
38261 N1C && N0.getOpcode() == ISD::AND &&
38290 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
38379 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
38408 return DAG.getNode(ISD::AND, DL, VT, NewShift, NewMask);
38739 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
38753 assert(N->getOpcode() == ISD::AND);
38796 Narrow->getOpcode() != ISD::AND &&
38873 case ISD::AND: FPOpcode = X86ISD::FAND; break;
39029 return DAG.getNode(ISD::AND, dl, VT, Inp, LShr);
39076 SDValue Parity = DAG.getNode(ISD::AND, DL, MVT::i32,
39112 assert(N->getOpcode() == ISD::AND && "Unexpected opcode!");
39192 DAG.getNode(ISD::AND, dl, MVT::i32, LHS, RHS));
39204 if (matchScalarReduction(SDValue(N, 0), ISD::AND, SrcOps) &&
39299 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND)
39299 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND)
39345 if (N1.getOpcode() == ISD::AND)
39349 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != X86ISD::ANDNP)
39676 if (ShAmt0.getOpcode() == ISD::AND &&
39683 if (ShAmt1.getOpcode() == ISD::AND &&
39724 if (ShAmt1Op1.getOpcode() == ISD::AND &&
40985 case ISD::AND:
41040 In = DAG.getNode(ISD::AND, DL, InVT, In, DAG.getConstant(Mask, DL, InVT));
41706 case X86ISD::FAND: IntOpcode = ISD::AND; break;
42070 return DAG.getNode(ISD::AND, SDLoc(N), VT, DAG.getBitcast(VT, Not),
42392 Vec = DAG.getNode(ISD::AND, DL, VT, Vec, BitMask);
42585 if (N0.getOpcode() == ISD::AND &&
42592 return DAG.getNode(ISD::AND, dl, VT,
42604 return DAG.getNode(ISD::AND, dl, VT,
42773 Cmp = DAG.getNode(ISD::AND, DL, CmpVT, Cmp1, Cmp2);
43115 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
43137 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
43382 Op = DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0),
43403 case ISD::AND:
43513 DAG.getNode(ISD::AND, DL, VT,
44603 InVecVT.getSizeInBits() == 256 && InVecBC.getOpcode() == ISD::AND) {
44758 if (VT == MVT::v1i1 && Src.getOpcode() == ISD::AND && Src.hasOneUse())
44924 case ISD::AND: return combineAnd(N, DAG, DCI, Subtarget);
45074 case ISD::AND:
45155 case ISD::AND:
lib/Target/X86/X86TargetTransformInfo.cpp 2639 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp
2640 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp
2646 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp
2647 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp
2648 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp
2649 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp
2657 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp
2658 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp
2659 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp
2660 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp
lib/Target/XCore/XCoreISelLowering.cpp 1648 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
unittests/CodeGen/AArch64SelectionDAGTest.cpp 168 auto N0 = DAG->getNode(ISD::AND, Loc, IntVT, Mask, UnknownOp);
190 auto N1 = DAG->getNode(ISD::AND, Loc, IntVT, Mask, UnknownOp);