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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc17959 { 271, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x440000120ULL, ImplicitList1, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #271 = ADC32mr
17999 { 311, 6, 0, 0, 944, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x40000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #311 = ADD32mr
18092 { 404, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x840000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #404 = AND32mr
18230 { 542, 6, 0, 0, 55, 0|(1ULL<<MCID::MayLoad), 0x28c0002120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #542 = BT32mr
18242 { 554, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ec0002120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #554 = BTC32mr
18254 { 566, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2cc0002120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #566 = BTR32mr
18266 { 578, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ac0002120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #578 = BTS32mr
18387 { 699, 6, 0, 0, 66, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xe40000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #699 = CMP32mr
18430 { 742, 6, 0, 0, 662, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2c40002120ULL, ImplicitList7, ImplicitList14, OperandInfo79, -1 ,nullptr }, // Inst #742 = CMPXCHG32rm
18934 { 1246, 6, 0, 0, 1046, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2c41002120ULL, ImplicitList7, ImplicitList14, OperandInfo79, -1 ,nullptr }, // Inst #1246 = LCMPXCHG32
18992 { 1304, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x41000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #1304 = LOCK_ADD32mr
19003 { 1315, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x841000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #1315 = LOCK_AND32mr
19022 { 1334, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x241000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #1334 = LOCK_OR32mr
19034 { 1346, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa41000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #1346 = LOCK_SUB32mr
19045 { 1357, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xc41000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #1357 = LOCK_XOR32mr
19354 { 1666, 6, 0, 0, 134, 0|(1ULL<<MCID::MayStore), 0x2240000120ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #1666 = MOV32mr
19413 { 1725, 6, 0, 0, 839, 0|(1ULL<<MCID::MayStore), 0x3c40004120ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #1725 = MOVBE32mr
19425 { 1737, 6, 0, 0, 134, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x3e40004020ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #1737 = MOVDIRI32
19450 { 1762, 6, 0, 0, 218, 0|(1ULL<<MCID::MayStore), 0x30c0002020ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #1762 = MOVNTImr
19611 { 1923, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x240000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #1923 = OR32mr
20247 { 2559, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x640000120ULL, ImplicitList1, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #2559 = SBB32mr
20326 { 2638, 6, 0, 0, 957, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2940002120ULL, ImplicitList90, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #2638 = SHLD32mrCL
20366 { 2678, 6, 0, 0, 957, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2b40002120ULL, ImplicitList90, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #2678 = SHRD32mrCL
20461 { 2773, 6, 0, 0, 944, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa40000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #2773 = SUB32mr
20572 { 2884, 6, 0, 0, 66, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x2140000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #2884 = TEST32mr
25817 { 8129, 6, 0, 0, 8, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1e00002020ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #8129 = VMREAD32mr
32838 { 15150, 6, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x3d80004020ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #15150 = WRSSD
32840 { 15152, 6, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x3d40004820ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #15152 = WRUSSD
32887 { 15199, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xc40000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #15199 = XOR32mr