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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc17868 { 180, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #180 = ADD64ri32_DB
17869 { 181, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #181 = ADD64ri8_DB
17923 { 235, 3, 1, 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #235 = SHLDROT64ri
17925 { 237, 3, 1, 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #237 = SHRDROT64ri
17969 { 281, 3, 1, 0, 1005, 0, 0x204011003aULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #281 = ADC64ri32
17970 { 282, 3, 1, 0, 925, 0, 0x20c003003aULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #282 = ADC64ri8
18009 { 321, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x2040110038ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #321 = ADD64ri32
18010 { 322, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c0030038ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #322 = ADD64ri8
18102 { 414, 3, 1, 0, 1, 0, 0x204011003cULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #414 = AND64ri32
18103 { 415, 3, 1, 0, 1, 0, 0x20c003003cULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #415 = AND64ri8
18247 { 559, 3, 1, 0, 59, 0, 0x2e8003203fULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #559 = BTC64ri8
18259 { 571, 3, 1, 0, 59, 0, 0x2e8003203eULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #571 = BTR64ri8
18271 { 583, 3, 1, 0, 59, 0, 0x2e8003203dULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #583 = BTS64ri8
19621 { 1933, 3, 1, 0, 1, 0, 0x2040110039ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #1933 = OR64ri32
19622 { 1934, 3, 1, 0, 1, 0, 0x20c0030039ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #1934 = OR64ri8
20048 { 2360, 3, 1, 0, 1019, 0, 0x304003003aULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2360 = RCL64ri
20078 { 2390, 3, 1, 0, 1017, 0, 0x304003003bULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2390 = RCR64ri
20149 { 2461, 3, 1, 0, 281, 0, 0x3040030038ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2461 = ROL64ri
20173 { 2485, 3, 1, 0, 281, 0, 0x3040030039ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2485 = ROR64ri
20223 { 2535, 3, 1, 0, 290, 0, 0x304003003fULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2535 = SAR64ri
20257 { 2569, 3, 1, 0, 1005, 0, 0x204011003bULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2569 = SBB64ri32
20258 { 2570, 3, 1, 0, 925, 0, 0x20c003003bULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2570 = SBB64ri8
20315 { 2627, 3, 1, 0, 290, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x304003003cULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2627 = SHL64ri
20355 { 2667, 3, 1, 0, 290, 0, 0x304003003dULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2667 = SHR64ri
20471 { 2783, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x204011003dULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2783 = SUB64ri32
20472 { 2784, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c003003dULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2784 = SUB64ri8
32897 { 15209, 3, 1, 0, 1, 0, 0x204011003eULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #15209 = XOR64ri32
32898 { 15210, 3, 1, 0, 1, 0, 0x20c003003eULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #15210 = XOR64ri8