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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc18138 { 450, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x806000a029ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #450 = BLCFILL32rm
18142 { 454, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x80a000a02eULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #454 = BLCI32rm
18146 { 458, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x806000a02dULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #458 = BLCIC32rm
18150 { 462, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x80a000a029ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #462 = BLCMSK32rm
18154 { 466, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x806000a02bULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #466 = BLCS32rm
18166 { 478, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x806000a02aULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #478 = BLSFILL32rm
18170 { 482, 6, 1, 0, 46, 0|(1ULL<<MCID::MayLoad), 0xbcd000402bULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #482 = BLSI32rm
18174 { 486, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x806000a02eULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #486 = BLSIC32rm
18178 { 490, 6, 1, 0, 46, 0|(1ULL<<MCID::MayLoad), 0xbcd000402aULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #490 = BLSMSK32rm
18182 { 494, 6, 1, 0, 46, 0|(1ULL<<MCID::MayLoad), 0xbcd0004029ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #494 = BLSR32rm
18209 { 521, 6, 1, 0, 660, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1880000121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #521 = BOUNDS32rm
18212 { 524, 6, 1, 0, 48, 0|(1ULL<<MCID::MayLoad), 0x2f00002121ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #524 = BSF32rm
18218 { 530, 6, 1, 0, 50, 0|(1ULL<<MCID::MayLoad), 0x2f40002121ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #530 = BSR32rm
18390 { 702, 6, 0, 0, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xec0000121ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #702 = CMP32rm
18480 { 792, 6, 1, 0, 768, 0|(1ULL<<MCID::MayLoad), 0xb40003821ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #792 = CVTSD2SIrm_Int
18508 { 820, 6, 1, 0, 769, 0|(1ULL<<MCID::MayLoad), 0xb40003021ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #820 = CVTSS2SIrm_Int
18518 { 830, 6, 1, 0, 768, 0|(1ULL<<MCID::MayLoad), 0xb00003821ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #830 = CVTTSD2SIrm
18519 { 831, 6, 1, 0, 768, 0|(1ULL<<MCID::MayLoad), 0xb00003821ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #831 = CVTTSD2SIrm_Int
18526 { 838, 6, 1, 0, 769, 0|(1ULL<<MCID::MayLoad), 0xb00003021ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #838 = CVTTSS2SIrm
18527 { 839, 6, 1, 0, 769, 0|(1ULL<<MCID::MayLoad), 0xb00003021ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #839 = CVTTSS2SIrm_Int
18614 { 926, 6, 1, 0, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #926 = EH_SjLj_SetJmp32
18615 { 927, 6, 1, 0, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #927 = EH_SjLj_SetJmp64
18623 { 935, 6, 0, 0, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e00005c21ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #935 = ENQCMD32
18626 { 938, 6, 0, 0, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e00005421ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #938 = ENQCMDS32
18794 { 1106, 6, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2000004821ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1106 = INVEPT32
18799 { 1111, 6, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2080004821ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1111 = INVPCID32
18801 { 1113, 6, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040004821ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1113 = INVVPID32
18928 { 1240, 6, 1, 0, 886, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80002121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1240 = LAR32rm
18941 { 1253, 6, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3140000121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1253 = LDS32rm
18961 { 1273, 6, 1, 0, 1053, 0|(1ULL<<MCID::Rematerializable), 0x2340000121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1273 = LEA32r
18967 { 1279, 6, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3100000121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1279 = LES32rm
18970 { 1282, 6, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2d00002121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1282 = LFS32rm
18976 { 1288, 6, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2d40002121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1288 = LGS32rm
19066 { 1378, 6, 1, 0, 886, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0xc0002121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1378 = LSL32rm
19071 { 1383, 6, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2c80002121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1383 = LSS32rm
19089 { 1401, 6, 1, 0, 183, 0|(1ULL<<MCID::MayLoad), 0x2f40003121ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #1401 = LZCNT32rm
19362 { 1674, 6, 1, 0, 62, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x22c0000121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1674 = MOV32rm
19414 { 1726, 6, 1, 0, 833, 0|(1ULL<<MCID::MayLoad), 0x3c00004121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1726 = MOVBE32rm
19423 { 1735, 6, 0, 0, 134, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x3e00004c21ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1735 = MOVDIR64B32
19489 { 1801, 6, 1, 0, 939, 0|(1ULL<<MCID::MayLoad), 0x2fc0002121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1801 = MOVSX32rm16
19490 { 1802, 6, 1, 0, 729, 0|(1ULL<<MCID::MayLoad), 0x18c0000121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1802 = MOVSX32rm32
19491 { 1803, 6, 1, 0, 939, 0|(1ULL<<MCID::MayLoad), 0x2f80002121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1803 = MOVSX32rm8
19516 { 1828, 6, 1, 0, 939, 0|(1ULL<<MCID::MayLoad), 0x2dc0002121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1828 = MOVZX32rm16
19517 { 1829, 6, 1, 0, 939, 0|(1ULL<<MCID::MayLoad), 0x2d80002121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1829 = MOVZX32rm8
19885 { 2197, 6, 1, 0, 268, 0|(1ULL<<MCID::MayLoad), 0x2e00003121ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #2197 = POPCNT32rm
20543 { 2855, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x806000a02fULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #2855 = T1MSKC32rm
20599 { 2911, 6, 1, 0, 320, 0|(1ULL<<MCID::MayLoad), 0x2f00003121ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #2911 = TZCNT32rm
20603 { 2915, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x806000a02cULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #2915 = TZMSK32rm
21822 { 4134, 6, 1, 0, 400, 0|(1ULL<<MCID::MayLoad), 0x1000b70003821ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4134 = VCVTSD2SIZrm_Int
21825 { 4137, 6, 1, 0, 874, 0|(1ULL<<MCID::MayLoad), 0xb50003821ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4137 = VCVTSD2SIrm_Int
21845 { 4157, 6, 1, 0, 1240, 0|(1ULL<<MCID::MayLoad), 0x1001e70003821ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4157 = VCVTSD2USIZrm_Int
21903 { 4215, 6, 1, 0, 401, 0|(1ULL<<MCID::MayLoad), 0x800b70003021ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4215 = VCVTSS2SIZrm_Int
21906 { 4218, 6, 1, 0, 986, 0|(1ULL<<MCID::MayLoad), 0xb50003021ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4218 = VCVTSS2SIrm_Int
21911 { 4223, 6, 1, 0, 401, 0|(1ULL<<MCID::MayLoad), 0x801e70003021ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4223 = VCVTSS2USIZrm_Int
22171 { 4483, 6, 1, 0, 400, 0|(1ULL<<MCID::MayLoad), 0x1000b30003821ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4483 = VCVTTSD2SIZrm
22172 { 4484, 6, 1, 0, 400, 0|(1ULL<<MCID::MayLoad), 0x1000b30003821ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4484 = VCVTTSD2SIZrm_Int
22176 { 4488, 6, 1, 0, 874, 0|(1ULL<<MCID::MayLoad), 0xb10003821ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4488 = VCVTTSD2SIrm
22177 { 4489, 6, 1, 0, 876, 0|(1ULL<<MCID::MayLoad), 0xb10003821ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4489 = VCVTTSD2SIrm_Int
22185 { 4497, 6, 1, 0, 1240, 0|(1ULL<<MCID::MayLoad), 0x1001e30003821ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4497 = VCVTTSD2USIZrm
22186 { 4498, 6, 1, 0, 1240, 0|(1ULL<<MCID::MayLoad), 0x1001e30003821ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4498 = VCVTTSD2USIZrm_Int
22199 { 4511, 6, 1, 0, 401, 0|(1ULL<<MCID::MayLoad), 0x800b30003021ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4511 = VCVTTSS2SIZrm
22200 { 4512, 6, 1, 0, 401, 0|(1ULL<<MCID::MayLoad), 0x800b30003021ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4512 = VCVTTSS2SIZrm_Int
22204 { 4516, 6, 1, 0, 986, 0|(1ULL<<MCID::MayLoad), 0xb10003021ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4516 = VCVTTSS2SIrm
22205 { 4517, 6, 1, 0, 986, 0|(1ULL<<MCID::MayLoad), 0xb10003021ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4517 = VCVTTSS2SIrm_Int
22213 { 4525, 6, 1, 0, 401, 0|(1ULL<<MCID::MayLoad), 0x801e30003021ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4525 = VCVTTSS2USIZrm
22214 { 4526, 6, 1, 0, 401, 0|(1ULL<<MCID::MayLoad), 0x801e30003021ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #4526 = VCVTTSS2USIZrm_Int
25924 { 8236, 6, 1, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1e40002021ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #8236 = VMWRITE32rm