reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/X86/X86GenAsmMatcher.inc

 9277   { 4677 /* movq */, X86::MOV64rm, Convert__Reg1_1__Mem645_0, AMFBS_None, { MCK_Mem64, MCK_GR64 }, },
23747   { 4333 /* mov */, X86::MOV64rm, Convert__Reg1_0__Mem645_1, AMFBS_None, { MCK_GR64, MCK_Mem64 }, },

gen/lib/Target/X86/X86GenDAGISel.inc

50732 /*107114*/      OPC_MorphNodeTo1, TARGET_VAL(X86::MOV64rm), 0|OPFL_Chain|OPFL_MemRefs,
53948 /*114325*/      OPC_MorphNodeTo1, TARGET_VAL(X86::MOV64rm), 0|OPFL_Chain|OPFL_MemRefs,

lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

  404       case X86::MOV64rm:

lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp

  455       buildCopy(LoadInst, X86::MOV64rm, LdDisp, StoreInst, X86::MOV64mr, StDisp,

lib/Target/X86/X86CallFrameOptimization.cpp

  623        DefMI.getOpcode() != X86::MOV64rm) ||

lib/Target/X86/X86CmovConversion.cpp

  540         if (Op == X86::MOV64rm || Op == X86::MOV32rm) {

lib/Target/X86/X86DomainReassignment.cpp

  656     createReplacer(X86::MOV64rm, X86::KMOVQkm);

lib/Target/X86/X86FastISel.cpp

  346     Opc = X86::MOV64rm;
  780           Opc = X86::MOV64rm;
 2685     case MVT::i64: Opc = X86::MOV64rm; RC = &X86::GR64RegClass; break;

lib/Target/X86/X86FrameLowering.cpp

  313       addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr),
  668   BuildMI(&MBB, DL, TII.get(X86::MOV64rm), LimitReg)
  721                            TII.get(X86::MOV64rm), X86::RCX),
  725                            TII.get(X86::MOV64rm), X86::RDX),
 1294         MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV64rm), X86::RAX),
 1324       addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), Establisher),

lib/Target/X86/X86ISelLowering.cpp

29406     BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
29453   BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
30246         BuildMI(*BB, MI, DL, TII->get(X86::MOV64rm), X86::RDI)
30606     unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
30711   unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
30829   unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
31022     unsigned Op = FPIs64Bit ? X86::MOV64rm : X86::MOV32rm;

lib/Target/X86/X86InstrFoldTables.cpp

  534   { X86::MOV64rr,              X86::MOV64rm,              0 },

lib/Target/X86/X86InstrInfo.cpp

  230   case X86::MOV64rm:
  531   case X86::MOV64rm:
 3113       return load ? X86::MOV64rm : X86::MOV64mr;
 3996   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
 4000   MIB->setDesc(TII.get(X86::MOV64rm));
 4907         if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
 5757   case X86::MOV64rm:
 5840   case X86::MOV64rm:

lib/Target/X86/X86InstructionSelector.cpp

  420       return Isload ? X86::MOV64rm : X86::MOV64mr;

lib/Target/X86/X86SpeculativeLoadHardening.cpp

 1570   case X86::MOV64rm:
 2520     BuildMI(MBB, InsertPt, Loc, TII->get(X86::MOV64rm), ExpectedRetAddrReg)