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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 2093 { 1301 /* csrr */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__regX0, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister }, },
2097 { 1319 /* csrrs */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
2103 { 1345 /* csrs */, RISCV::CSRRS, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
2212 { 1890 /* frcsr */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3__regX0, AMFBS_HasStdExtF, { MCK_GPR }, },
2213 { 1896 /* frflags */, RISCV::CSRRS, Convert__Reg1_0__imm_95_1__regX0, AMFBS_HasStdExtF, { MCK_GPR }, },
2214 { 1904 /* frrm */, RISCV::CSRRS, Convert__Reg1_0__imm_95_2__regX0, AMFBS_HasStdExtF, { MCK_GPR }, },
2215 { 1909 /* frsr */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3__regX0, AMFBS_HasStdExtF, { MCK_GPR }, },
2309 { 2236 /* rdcycle */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3072__regX0, AMFBS_None, { MCK_GPR }, },
2310 { 2244 /* rdcycleh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3200__regX0, AMFBS_IsRV32, { MCK_GPR }, },
2311 { 2253 /* rdinstret */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3074__regX0, AMFBS_None, { MCK_GPR }, },
2312 { 2263 /* rdinstreth */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3202__regX0, AMFBS_IsRV32, { MCK_GPR }, },
2313 { 2274 /* rdtime */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3073__regX0, AMFBS_None, { MCK_GPR }, },
2314 { 2281 /* rdtimeh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3201__regX0, AMFBS_IsRV32, { MCK_GPR }, },
gen/lib/Target/RISCV/RISCVGenAsmWriter.inc 1724 case RISCV::CSRRS:
gen/lib/Target/RISCV/RISCVGenDAGISel.inc12107 /* 22527*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::CSRRS), 0|OPFL_Chain,
12116 /* 22546*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::CSRRS), 0|OPFL_Chain,
12126 /* 22567*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::CSRRS), 0|OPFL_Chain,
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc 818 case RISCV::CSRRS:
lib/Target/RISCV/RISCVISelLowering.cpp 1128 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), HiReg)
1131 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), LoReg)
1134 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), ReadAgainReg)