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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc 3296 { 388, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo71, -1 ,nullptr }, // Inst #388 = BCDCFNo
3297 { 389, 3, 1, 4, 168, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo71, -1 ,nullptr }, // Inst #389 = BCDCFSQo
3298 { 390, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo71, -1 ,nullptr }, // Inst #390 = BCDCFZo
3299 { 391, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #391 = BCDCPSGNo
3300 { 392, 2, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo73, -1 ,nullptr }, // Inst #392 = BCDCTNo
3301 { 393, 2, 1, 4, 166, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo73, -1 ,nullptr }, // Inst #393 = BCDCTSQo
3302 { 394, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo71, -1 ,nullptr }, // Inst #394 = BCDCTZo
3303 { 395, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo71, -1 ,nullptr }, // Inst #395 = BCDSETSGNo
3304 { 396, 4, 1, 4, 165, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo74, -1 ,nullptr }, // Inst #396 = BCDSRo
3305 { 397, 4, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo74, -1 ,nullptr }, // Inst #397 = BCDSo
3306 { 398, 4, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo74, -1 ,nullptr }, // Inst #398 = BCDTRUNCo
3307 { 399, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #399 = BCDUSo
3308 { 400, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #400 = BCDUTRUNCo
4609 { 1701, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1701 = VCMPBFPo
4611 { 1703, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1703 = VCMPEQFPo
4613 { 1705, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1705 = VCMPEQUBo
4615 { 1707, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1707 = VCMPEQUDo
4617 { 1709, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1709 = VCMPEQUHo
4619 { 1711, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1711 = VCMPEQUWo
4621 { 1713, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1713 = VCMPGEFPo
4623 { 1715, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1715 = VCMPGTFPo
4625 { 1717, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1717 = VCMPGTSBo
4627 { 1719, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1719 = VCMPGTSDo
4629 { 1721, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1721 = VCMPGTSHo
4631 { 1723, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1723 = VCMPGTSWo
4633 { 1725, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1725 = VCMPGTUBo
4635 { 1727, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1727 = VCMPGTUDo
4637 { 1729, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1729 = VCMPGTUHo
4639 { 1731, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1731 = VCMPGTUWo
4641 { 1733, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1733 = VCMPNEBo
4643 { 1735, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1735 = VCMPNEHo
4645 { 1737, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1737 = VCMPNEWo
4647 { 1739, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1739 = VCMPNEZBo
4649 { 1741, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1741 = VCMPNEZHo
4651 { 1743, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1743 = VCMPNEZWo
4993 { 2085, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, ImplicitList16, OperandInfo289, -1 ,nullptr }, // Inst #2085 = XVCMPEQDPo
4995 { 2087, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, ImplicitList16, OperandInfo289, -1 ,nullptr }, // Inst #2087 = XVCMPEQSPo
4997 { 2089, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, ImplicitList16, OperandInfo289, -1 ,nullptr }, // Inst #2089 = XVCMPGEDPo
4999 { 2091, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, ImplicitList16, OperandInfo289, -1 ,nullptr }, // Inst #2091 = XVCMPGESPo
5001 { 2093, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, ImplicitList16, OperandInfo289, -1 ,nullptr }, // Inst #2093 = XVCMPGTDPo
5003 { 2095, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, ImplicitList16, OperandInfo289, -1 ,nullptr }, // Inst #2095 = XVCMPGTSPo