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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc19864 { 3802, 7, 1, 8, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo407, -1 ,nullptr }, // Inst #3802 = V_MFMA_F32_16X16X8BF16
19872 { 3810, 7, 1, 8, 22, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo407, -1 ,nullptr }, // Inst #3810 = V_MFMA_F32_4X4X2BF16
19874 { 3812, 7, 1, 8, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo407, -1 ,nullptr }, // Inst #3812 = V_MFMA_I32_16X16X16I8
19878 { 3816, 7, 1, 8, 22, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo407, -1 ,nullptr }, // Inst #3816 = V_MFMA_I32_4X4X4I8
30596 { 14534, 7, 1, 8, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo407, -1 ,nullptr }, // Inst #14534 = V_MFMA_F32_16X16X8BF16_vi
30604 { 14542, 7, 1, 8, 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo407, -1 ,nullptr }, // Inst #14542 = V_MFMA_F32_4X4X2BF16_vi
30606 { 14544, 7, 1, 8, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo407, -1 ,nullptr }, // Inst #14544 = V_MFMA_I32_16X16X16I8_vi
30610 { 14548, 7, 1, 8, 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo407, -1 ,nullptr }, // Inst #14548 = V_MFMA_I32_4X4X4I8_vi